DFT Digest

If you’ve ever been involved with device test or design for test, you’re very likely familiar with at least one of these acronyms - most probably WGL (Waveform Generation Language). If you’ve been in practice in the last 10 years, you’ve at least heard of STIL (Standard Test Interface Language).

How much do you know about CTL (Core Test Language)? If you’re like me, not a ton. I haven’t worked on chips that have integrated a lot of hard IP. Hey, not everyone gets to work on the really big ones. But I do know the industry’s going that way. It’s a huge topic. You can’t turn a page in a trade mag or visit an engineering website without seeing something about the quality of IP. There’s many facets to the overall quality of something like that, but our job as DFT folk is to know if you can test it.

I’d be interested to hear from anyone reading if you’ve used IEEE 1500 compliant cores, and what your experience has been in using them!

Anyway, back to CTL - it’s the newest in the evolution - in the narrowest sense - of formats/languages describing test data. And, it’s not all that new, really. It was approved as IEEE Standard 1450.6-2005 in 2005. However, it’s much more than just test data (which is what STIL, or Standard Test Interface Language, is). CTL really defines a core from a test perspective, and how that core may be integrated into an SoC. It describes the test structures included in the core and how to communicate with them.

More after the click..

“Core Test Language (CTL) is the official mechanism for describing IEEE 1500 wrappers and test data associated with cores. CTL is defined in IEEE P1450.6â„¢ and was originally begun as part of the development of IEEE Std 1500.”

That, according to the 1500 website. There’s the key. It’s not just a test language; it belongs to the standardized test structures defined in IEEE 1500.

Again, I personally have had no experience with CTL or embedded cores that contain 1500 compliant wrappers, but it’s clear to me that for SoCs that rely on large amounts of IP from multiple vendors, a consistent interface to these blocks would be highly desirable. And if you look around, there’s a lot to these two intertwined standards. I’m going to just link a few. You’ll have to

For more information, there are a couple of articles here and here. There are also a couple of books:

First off, here’s a new book:

The Core Test Wrapper Handbook: Rationale and Application of IEEE Std. 1500

and then there’s

CTL for Test Information of Digital ICs

Let me know if you know of other good sources of information on-line…