DFT Digest

Now let’s face it: Design for Manufacturing (DFM) is the hottest sector of the EDA industry. Everything else is, well, meh. From what I can gather, there are those who feel the sector of the future should be ESL, but it’s my opinion that true system-level design is many years out. Let designers get accustomed to SystemVerilog, I say. DFM, on the other hand is an immediate need. It cuts to the bottom line of profitability for every semiconductor company pursuing leading edge products. These are problems the industry needs to solve.

I started writing this post a few days ago, and let it lie as a near casualty in my recent fight with blogging burn-out. In the mean-time, John Busco wrote a post on Sramana Mitra’s contention that DFM/DFY provider PDF Solutions needs to find an eligible EDA company (or vice versa) for company nuptials. John wonders just how big the DFM sector can get, when it’s main customers are fabs and big IP providers. That’s a good point.

But I still contend that this sector is crucial to semiconductor companies, fabless or not. Very few chips, without it, will make it out of the fab alive. And that’s no way to run a chip business. So maybe Sramana is right - DFM/DFY companies need to be hooked up with EDA vendors as part of their portfolio. The business model should be different in that the actual benefactors (chip companies) will be using the tool, through the tool owner (the fab) - unless the chip company is big enough and pushes enough volume to warrant having their own tool. I rent my ski equipment, if you get the analogy.

So what does this have to do with Design-for Testability? I’ve mentioned a few times that DFT/Test are essential to a successful DFM strategy. It should be obvious - I mean, without a feedback mechanism, and data collection, how can yield be improved?

In a new article: DFT, ATE drive yield improvement, in T&M World written by Ajay Khoche of Verigy and Wu Yang of Mentor, the benefits and challenges of leveraging structural test results by linking them back to the design itself. The EDA industry is actively working to create these linkages - companies that provide yield analysis tools should be able to take scan failure data and attempt to automatically isolate the failing circuitry in the schematic, and ultimately, the layout. Yet another reason for DFM/DFY tools to be part of a EDA vendor’s portfolio, because, as of now, standard linkages are not yet in place.