DFT Digest

I’ve just been searching around for DFM related material, and I keep seeing DFT being mentioned as a critical component of DFM, so I’ll just keep on mentioning it here.

The latest article I find (and I guess it’s not new, but it’s dated 7/6/2006, which is new enough) is by Ron Wilson at EDN, and it contains a sidebar on DFT and DFM, but from a different angle than what I blogged on yesterday (i.e., test as measurement/analysis). This piece discussed it more from the notion that design-for-test must be planned and executed, keeping in mind the systematic process variations that will screw the designer if he/she does not consider DFM.

Citing a marketing head for LogicVision, the article noted that “IR drops can be significantly smaller than they would be during sustained operation of the same circuit. So, the one-shot test may miss a delay fault that is IR-drop-related simply because launching one edge didn’t sufficiently stress the supply grid.” Which is probably a very good point. As you might expect, LogicVision claims to have a tool that creates patterns that mitigate the issue.

The other significant point, IMHO, related to the fact that failure modes are changing with geometry shrinkage, but fault modeling technology is not keeping up. It would be nice to be able to utilize a predictive DFT methodology that uses analysis of both the layout and timing models to come up with a more efficient test set.

Hmmm… maybe soon?