DFT Digest

DAC is just over a week away – and I’ve been making cracks here and there about the lack of test-related material.  So I’d like to welcome a counterpoint from Dr. Yervant Zorian, DAC EDA Industry Chair; Vice President and Chief Scientist at Virage Logic (the cv supplied by him – I’m here to tell you his involvement in, and contributions to the EDA and DFT/Test community are much more extensive)

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Lest you think that test is an overlooked design discipline within the Design Automation Conference Technical Program, I’d like to direct your attention to two sessions that should be thought-provoking and insightful discussions on test methodologies.

Session 41, to be held Thursday, July 30, is titled, “Targeted Test and Diagnosis,” and will address the importance of targeting the right faults with the appropriate test method. Four papers will explore advances in improved targeting methods for a range of test topics, such as digital test generator, IC diagnosis, embedded DRAM BIST and RF testing.

While many within the design community see an artificial gap between design and test, test is often a methodology that helps solve silicon design challenges or spawns new EDA methodologies.

Consider just how the complexity of multi-million gate chips adds to the difficulty of guaranteeing error-free designs before tapeout. Validating the first silicon samples and searching for design bugs post-silicon rely heavily on the design-for-test (DFT) infrastructure developed and inserted in the designs for aiding manufacturing test.

As a consequence, there has been an increased number of papers at DAC on using DFT extensions for post-silicon validation and debugging. Papers on post-silicon debugging, for example, will be presented Wednesday in Session 22 titled, “Speed Path Identification and Silicon Debug.”

Many of the advancements in test automation have been reported for the first time at DAC. Using sophisticated automated methods, they have gradually evolved to cope with the complexity brought by nanometer process technologies and multi million-gate designs.

In recent years, test has been used also as an enabling technology for yield enhancement. Learning from defective samples can help improve the design –– through performance tuning, for example –– CAD tools, process development, manufacturing, and, in many cases, the test itself. All contribute to yield optimization and depend in large part on the advancements in the test technology.

In addition to Sessions 41 and 22, the technical program will include another 50 research paper sessions and 152 talks that cover analog/mixed-signal/RF, DFM, interconnect and reliability, low power, physical design synthesis, FPGAs, system and embedded design.

The three-day User Track is a new feature and offers attendees more than 40 presentations and 42 posters focused on the latest in tool use and methodologies. Management Day, sponsored this year by Cadence, will be held Tuesday and provides managers with timely information to help them make decisions where business and technology intersect.

In addition, various other papers, panels, User Track and Management Day sessions cover test technology challenges, solutions and trade-offs. And, the DAC Exhibit Floor is a showplace of key EDA and IP providers in the Design-for-Test domain where products and services in the DFT industry are actually showcased and demonstrated.

Please plan to join me and other members of the design automation and test community for this year’s DAC to see for yourself that DAC and test are not that far apart after all.

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This year’s DAC will be held July 26-31 at the Moscone Center in San Francisco. Register now at: DAC.