DFT in the 3rd dimension (or, “how do we go up from here?”)
Sometimes a post just begs to be written. Subconsciously, little reminders crop up in your input stream (a.k.a. eyes and ears) that prod you into doing something. Last week, like a Hitchcock blonde, it seemed like every time I turned around, something referring to 3-D technology popped out at me. I think it started when I began searching for material on JTAG implementations for MCMs…
Then, about a week back, John Blyler from ChipDesign tweets the following:
Oct 2, 2009 – Stacked die, SiP, 22nm, EDA numbers, verifying verification, going postal, 3D and more. http://bit.ly/xsgvw #chipdesign
The stacked die and SiP sticks in my head. To be honest, it took a little looking to find the actual article (here), because the link at the blog where the short-url above leads you is broken. It’s an interview with a panel of experts about the challenges of design at 22nm.
Then earlier this week, Rick Nelson, of EDN and and Test & Measurement World, tweets this:
“BIST gives way to built-in self-everything with 3-D ICs; test event to reach out to designers, says Verigy’s Volkerink: http://bit.ly/2OXUf2“
This was a pointer to Nelson’s second interview pertaining to the upcoming International Test Conference, with Erik Volkerink, of Verigy. In his first interview of Program Chair Bill Eklow (and mine), 3D technology was also brought up as a hot topic.
Later, as I reached into my mailbox at home, after work, I retrieved the latest copy of Chip Scale Review, containing two cover stories, 3D: The Latest Developments, and Hybrid Bonding of 3D Stacked ICs. After opening the magazine, I found a couple more interesting articles on test as well, including one on Protocol-Aware ATE (although the term wasn’t used in the article). You can read the whole magazine at their website.
So how many times can this topic smack me in the forehead before I pay attention? Well, I guess in this case, a few. But OK, I get it. So what did I get from all this? Well first, if you follow the right people on Twitter, you’re bound to find some interesting things you may not have otherwise.
But on the subject of 3D: It seems to be one of the next pushes in packing more real estate into the same real estate (sort of like Japan – when you can’t build out, build up). But more importantly to us folks with job titles that include the word test, it presents as many access challenges (0r more) as any of the other measures that have been taken over the years to further integrate more functions into smaller spaces.
And if I had to predict, I’d say that JTAG/boundary scan (IEEE 1149.1 and its follow-ons) will be a key player in meeting these challenges. What do you think?
Stumble It!
Hello John,
I think it is very clear that JTAG-based (and 1149.7, so-called compact JTAG) testing will be a key player in 3-D test. 1149.7, with it’s broadcast-star architecture is more appropriate in that it allows multiple 1149.1 Test Access Port (TAP) controllers to be dealt with in an addressable network manner. For example, this would be directly applicable when each die in a stack has its own TAP.
Another emerging standard, P1687 IJTAG, uses boundary scan (1149.1 or 1149.7) for access to 3D chips. The targets for this access are the test and measurement instruments that are embedded on-chip.
Please see a full article at SoC Central written by my colleague, Al Crouch. http://www.soccentral.com/results.asp?EntryID=29799
Thanks for the comment Scott – and thanks for the pointer to the Al Crouch article. I’ve always enjoyed his writing style – informal, conversational… it’d be great to have him do a guest post here at DFT Digest sometime.
He does a great job of pulling together the different specs and how they would help the 3D test solution. Funny, just to hammer home the point of my post, I received the new issue of Design & Test magazine yesterday – a special issue on 3D IC Design and Test.
Well whadya know?