DFT Digest

Where designers might say, “how do I build this next big monster that the marketing department is demanding?”, we design-for-test engineers are asking the obvious related question: “How am I going to test this next big monster that the designers are slapping together?” Some days I find myself wishing that we’d do the same chip over so I could dive even deeper into the details of any lost coverage and nail everything down perfectly. No such luck. Perhaps gathering lessons learned will always be #1 on my list of DFT Strategies for SoCs.

So many things change from one design to another: designs get bigger and require more power, lithography gets smaller, test access decreases, or practically disappears, techniques and standards are developed, EDA tools for facilitating test improve and proliferate.  Top that with the fact that when a design is given over for DFT implementation varies quite a bit from organization to organization.  In some cases the strategy becomes, “Do what you can with what you’ve been given.”

If you’re lucky enough to be involved in the design from the beginning of the architecture design, you can have the most influence, which hopefully translates into the best result – as long as you’re able to stay close to the project from start to finish.  In this case, I think I would suggest a “top-down architecture, bottoms-up implementation” approach.

You can address your main test methodologies, test access, partitioning, power issues, etc. from the top down.  Determine your target ATE and the limitations it will bring to your DFT plan.  Are you going to use scan, BIST or both?  What other types of test are appropriate?  If you have memory, will you need repair?  How will the analog blocks interface to the digital blocks?  How can you use the digital blocks to help test the analog blocks?

Implement the methodologies and take care of any rule violations and fault coverage issues from the bottom, and work your way up.  A good fault coverage at the block level will translate to a better coverage at the top.  Also, verify at the block level, and your job will be easier when running top-level verification – any problems you encounter will be only between blocks and in the top-level logic – nicely narrowed down for a quick solution.

DFT is fun – good luck!