DFT Digest

[editors note: This post is fourth in a regular series of featured contributions from Stephen Pateras of LogicVision]

Probably one of the hottest design topics these days is power minimization. This is not surprising given how much we love our high-performance mobile and wireless toys. But what does that mean to BIST solutions? Well, low power requirements affect BIST solutions (and DFT in general) in two separate ways. First, it’s important to ensure that any functional power constraints are met (or at least adequately managed) during BIST execution. Second, it’s necessary to ensure that a BIST solution is compatible with whatever low-power design techniques are being used. Since my last post was on memory repair, I’ll complete that topic here with a discussion on power management. In my next post, we’ll turn to logic BIST features and techniques for supporting low power designs.

If you recall from John’s post on Memory Repair Basics, the self-repair process involves determining the repair info for each repairable memory on the die using built-in repair analysis (BIRA) logic and then shifting and burning this info into a centralized eFuse array. Then each time the device is powered up, the repair info is shifted out of the eFuse array and back into each memory’s repair register. This last step typically uses a single serial shift register that is routed to all memories that have redundancy. Using a single serial register, greatly minimizes routing overhead and simplifies the management of the repair data. This simple approach, however, breaks down when voltage islands are used.

Use of voltage islands, an increasing popular power management approach, involves using a separate supply voltage for each core (or, possibly, group of cores) within a design. Each resulting island can then be shut down when it isn’t needed and re-activated when it is. As you might have guessed, all of this powering up and down activity poses some serious problems with repairable memories. When a sleeping island is re-activated, the repair information for the repairable memories in that island will have been lost and will need to be reloaded. The challenge here is twofold: the reloading has to occur without disrupting the already active islands, and the reloading can’t be affected by the fact that some islands may still be inactive.

To handle these constraints, the self-repair process described above has to be augmented to provide at least one repair shift register for each voltage island. Each shift register can be of arbitrary length. A functional power management unit indicates to the self-repair controller which shift register(s) need to be loaded. The other shift registers are kept in a stable state as they might contain repair information of active voltage islands. When multiple islands are re-activated, the controller will generally need to load them sequentially according to a default priority defined at design time. The operation is sequential since all repair information is typically stored in the same eFuse array. If the loading order needs to be changed, the power management unit simply needs to re-activate each island one at a time in the desired order. One possible performance improvement suggestion is to have a flag set by the controller as soon as a repair register has been loaded so that critical memories can be used immediately–without waiting for all memories to be repaired.

[Steve Pateras is VP of marketing at LogicVision. Steve performed his graduate work in test and has spent his entire career involved in either using, defining, or marketing DFT and BIST products and technologies]