DFT Digest

It feels good to be right… it does happen sometimes.  Back in May, when Mentor Graphics announced its intentions to acquire LogicVision, most folks writing about the deal pointed out a significant overlap in the product offerings of the two companies – surely the move didn’t make much sense (but to be fair, none of them know much about the DFT market).  I first blogged the news here, and again here, in response to the overlap arguments. My feeling was that LogicVision brought strengths in some product areas where Mentor was flagging.  And, I was right.

The summer has passed; the deal has closed.  So I asked Joe Sawicki, VP and GM of Mentor’s Design-to-Silicon Division, if he was ready to share more detail as to the direction of their DFT products.  In a phone conversation with Mr. Sawicki and Greg Aldrich, Marketing Director of the Silicon Test Solutions group, we talked about what DFT at Mentor looks like after bringing in LogicVision.  Sawicki started off the call by re-iterating his belief that Test is an important link in the IC design chain.

Overlap? Well, yes, and no… Yes, there was product overlap, but when one considers strengths, and in particular, revenue, there was “very little overlap”.   According to Aldrich, LogicVision commands over 50% of the available BIST market, while Mentor has over 50% of the ATPG market.   Obviously Mentor’s focus has been on the ATPG-related tools, whereas LogicVision is (was) a BIST  company.   I think that from a DFTer’s point of view,  this is fairly obvious, and I said so in my second post on the merger.

Mentor plans to go forward with LogicVision’s BIST tools (memory and logic BIST), and ETBoundary, LogicVision’s boundary scan design (BSD) tool, since BSD infrastructure is used as the window to most BIST implementations.  These are tools common to both companies, and decisions have been made to supplant existing tools for incoming tools – although Aldrich did make a point of saying that existing tools will continue to be supported.

Mentor seems ready to try to put an end to the age-old “BIST vs. ATPG” debate.  Now, with both types of tools in hand, what’s the plan?  According to Aldrich, “our roadmap and our vision has been, for the last 18 months, to combine the technologies… to create a merged solution of logic BIST and embedded compression”.  A single flow.

This seems like the steepest hill to climb.  ATPG and LBIST proponents have been poking at each other for years.  Only in the last few years have the techniques begun to be used in conjunction with each other.  One hears of using ATPG patterns to ‘top-up’ LBIST coverage, or BIST cores being integrated into scanned SoCs with the help of IEEE 1500, or other isolation wrappers, but it’s certainly not an out-of-the box flow.

Mentor and LogicVision took their first step in integrating the two technologies in 2007, when LogicVision’s ScanBurst product was announced.  It will be interesting to see how long it takes for them to take it the rest of the way: an SoC-level planning tool, maybe? (Let’s put BIST here, compression there, plop down this scanned IP-core here, and then tie it all up with BIST, for system-level use!)

Slaying the unruly AMS-test dragon – For me, one of the more interesting facets of LogicVisions BIST products are the  Analog/Mixed-Signal (AMS) BIST IP/tools:  ETSerdes and ETPLL.   Mentor had no tools in this space, and  Aldrich claims they see much interest in these products as their customers struggle with high speed I/O and analog test.  He admits that Mentor is new to this space, and plans to continue putting effort into these tools.

Attempts at automating AMS-test have come and gone.   Despite ‘Whatever happened to‘ questions out there, it hasn’t been completely dormant.  For example, read a guest post on Paul McLellan’s ‘EDA Graffiti’ blog by CEO of a company called ATEEDA, who is marketing an AMS-BIST tool called LinBIST.

Then there is the subject of post-silicon tools: Mentor’s YieldAssist and LogicVision’s Silicon Insight.  According to Aldrich, there is plenty of synergy here.  YieldAssist has focused mostly on data-gathering for diagnosis and yield enhancement, using ATPG data, of course.  s Silicon Insight, likewise, leverages BIST infrastructure for interactive debug.  There seems to be plenty of opportunity here for interactive debug of ATPG vectors, as well as applying BIST failure data to yield improvement.

ITC season is upon us, and I’m sure there will be more detail in the PR-mill.  Beyond a challenging task of marrying ATPG and BIST technologies, it’s also interesting to note that this approach even more highly differentiates Mentor and  Synopsys with respect to DFT.   Mentor is attacking the higly integrated SoC environment, whereas Synopsys is specifically trying to address the small geometry problems.

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