DFT Digest

It may take me a couple of weeks to crawl through what I saw and heard in my 3-4 days at ITC this year – many of the articles written by the trade press have already (I’ll be linking to them as I see them).  Likely by next week, you won’t see any more ITC stories.  But you will here – DFT Digest – the gift that keeps on giving?   he he… well one thing for sure, your not likely to find any personalized accounts in those stories as you will in mine.  That’s what makes blogging fun!

Q: So what do steak, jugglers and analog fault models have in common?

A: Tuesday.

I already blogged about the plenary session on Tuesday, and I did mention that I would blog the panel session I attended,  Can EDA Help Solve Analog Test and DFT Challenges? So,  first things first.  The panel.  I’ll link again to Ron Wilson’s take.

As I sat watching the panelists presenting their case, a feeling of déjà vu crept over me like the effects of the jalapenos in last night’s enchiladas (as they say, there’s good déjà vu, and there’s bad déjà vu). I’d heard all this before: 13 years ago. In a former life I was a mixed-signal test engineer, working for a company that had been  acquired by TI. At the time, we were having quality problems with some of our higher volume designs, which were implemented in BiCMOS. To make a long story fit in a blog post, my bosses set me to work to try and quantify, in any way possible, our test coverage.

Despite some interesting new research (at the time), there certainly wasn’t anything ready in the analog fault domain to use in the industry.  Luckily for us, these circuits were somewhat manageable, at least small enough that the schematics were routinely printed out for reference.  So,  we used them – we locked designers in conference rooms with test engineers for 2-3 days at a time, asking the same question over and over again: “If this circuit broke, would we see it in any of the tests we have on the ATE? OK, cool – how about this one?”  Until we ran out of schematics.

I know, you’re thinking – that’s plumb loco!  How tedious can it get?  OK – you’re right.  But it worked.  In case after case, we came up with either new tests to implement or ideas for control/observability that could go into the next design.  And we cut our DPPM by an order of magnitude.  All for the lack of an analog fault model.  Craig Force, the first panelist to speak, remembers those days well – which is probably why he says he had that same feeling in his stomach when asked to participate.  13 years, no progress.

The lack of an acceptable fault model was only one of the barriers mentioned by the panel.  Irregularity of custom analog designs make it nearly impossible to take a defect oriented approach to testing them: they’re not normally cookie-cutter-like repeated structures, they’re not usually very dense, so a manufacturing defect that would most likely kill a memory structure every time, may not bother the analog circuit at all.  So as panelist Steve Sunter points out, the best shot we have today in automating mixed-signal/analog (MSA) test is to put the tester on the chip and test the circuit similarly as you would with external ATE – against the datasheet specs.

Poor Rohit Kapur of Synopsys… whoever corralled him onto this panel owes him a beer.  He pleaded ignorance from the start, being a digital guy on a panel of MSA guys, but did manage to offer that as long as whatever analog things that need to be tested could be digitized,  then the EDA companies would be glad to take that data and automate the comparison against the spec limits. When asked by Force why all the bright young minds that the EDA companies were grabbing out of our universities couldn’t innovate a solution, Kapur replied that customers innovate, EDA companies automate.

Karim Arabi of Qualcomm and Sanjiv Taneja of Cadence provided additional customer and EDA perspective on the problem, and as it turned out everyone pretty much agreed that the industry needs to go back to the drawing board and find a fault model that can be come the basis for some kind of coverage quantification and test generation.

So that’s analog fault models… what about the steak and jugglers?  Well remember I was having a hard time deciding on the two simultaneously occurring EDA vendor receptions?  Well I cheesed out and split the difference, catching a nice steak dinner w/ Synopsys, and some juggling performers at the Mentor reception.   It was a nice evening!

Coming up in the next few blog posts: my conversations with the EDA vendors!   Stay tuned…