DFT Digest

[editors note: This post is fifth in a regular series of featured contributions from Stephen Pateras of LogicVision]

As luck (or Murphy) would have it, just when we thought we had the at-speed logic test problem licked, along comes all these power problems. But no need to panic (at least not for this…) because as it turns out, there are a bunch of techniques you can use to deal with this growing challenge.

In a nutshell, at-speed logic test techniques, both BIST and ATPG-based by the way, can cause power variations that don’t occur during functional operation. These variations often cause inaccurate testing or possibly worse, harm to the device under test. These power variations come in two (not very appetizing) flavors: instantaneous power variations, typically seen at the beginning of a pattern or timing sequence, and average power variations, due to different circuit activity levels. The instantaneous flavor is often referred to as a di/dt issue because a sudden change in circuit activity caused by the application of a test pattern or sequence causes a sudden change in the current through the device power network. This sudden current change is opposed by the inherent inductance in the network and causes a drop in the voltage level seen by the transistors. The average power problem is often referred to as an IR-drop issue. Here, increased circuit activity during test causes higher average current which due to the resistance of the power network causes once again a drop in the voltage level seen by the transistors. In both cases, the drop in the voltage level at the very least affects circuit timing and thus the quality of any at-speed tests. In the worst case, the drop will cause the circuit to fail and result in throwing away a possibly good part.

To avoid the IR-drop issue, the test approach has to go Green and use less power. There are a number of simple things and a few less simple (er, complex) things that can be done to achieve this. The simple things include turning off I/Os, de-selecting embedded memories, and applying tests to the device in stages (usually by hierarchical region) while disabling the clocks and/or loading constant values in blocks not currently under test.. A more complex approach is to limit the amount of circuit toggling activity that occurs during scan as this tends to be much higher than during functional operation. One way to achieve this is to reduce how often consecutive bit values toggle within each scan pattern. This can be done during the test pattern generation process if ATPG patterns are used or by controlling (biasing) the output of the PRPG if logic BIST is being used. Another approach is to gate the functional output of high-fanout flip-flops during the scan process. This however results in additional overhead and affects the quality of at-speed tests on some of the longer paths.

Avoiding the instantaneous power issue is a little trickier. There are two general approaches to this: wait long enough for the di/dt effect to subside before capturing the test result OR ramp up activity slowly enough to avoid the di/dt effect altogether. Consider the following: the typical approach to apply an at-speed scan test is to load a pattern using a relatively slow scan clock (say at 50 MHz) and then once the pattern is loaded apply two consecutive functional clock cycles (often in the 100s of MHz range) to perform the at-speed launch and capture. The di/dt effect occurs here due to the sudden transition from the scan activity to the much faster functional clock pulses. The problem is well documented in several papers including this one from Intel. One way to avoid this problem is to use a technique called BurstMode which allows multiple functional clock cycles to be applied after the scan operation but before the test response is captured. The additional functional clock cycles provide enough time for the di/dt effect to subside before capturing the circuit response.

Power constraints during test are here to stay. There are many existing techniques and many more in development for dealing with these pesky issues. So the bigger challenge will be to keep current on available solutions and then choose the right mix for your design.

[Steve Pateras is VP of marketing at LogicVision. Steve performed his graduate work in test and has spent his entire career involved in either using, defining, or marketing DFT and BIST products and technologies]