DFT-in-the-News, 11/02/2008
Santa Clara, California – International Test Conference - October 30th, 2008 – Intellitech Corporation, www.intellitech.com, the leader in lowering electronic product costs through IEEE 1149.1/JTAG, has announced UltraTAP-BT, a Bluetooth enabled IEEE 1149.1/JTAG pod with non-volatile test program and failure memory.
Teseda and Mentor Graphics Partner to Speed Defect Diagnosis
PORTLAND, Oregon ─ October 24, 2008─Teseda Corporation, a leading silicon validation and failure analysis diagnostic company, announced today that they have partnered with Mentor Graphics to link Mentor Graphic’s YieldAssist toolset with the Teseda Diagnostic Environment.
Cadence Encounter Test helps Hitachi Improve Product Quality and Lower Manufacturing Test Cost
SAN JOSE, Calif., 29 Oct 2008 - Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced today that its unique test technologies have enabled Hitachi Ltd., in the hardware domain of Information & Telecommunication Systems, to cost-effectively produce high-performance large scale integrated circuit (LSI) devices in volume with the lowest number of test escapes or defects achieved by Hitachi to date.
ASSET joins Synopsys in-Sync™ Program to Advance Embedded Instrumentation Tools
Richardson, TX (October 28, 2008) - ASSET® (www.asset-intertech.com), the leading supplier of open tools for embedded instrumentation, has joined Synopsys’ in-Sync™ program for third-party suppliers of EDA-related products. Synopsys is a world leader in software and IP for semiconductor design and manufacturing.
Teradyne and JTAG Technologies Provide Test Solution for Advanced Digital Networks
NORTH READING, Mass., - October 28, 2008 - Teradyne, Inc. (NYSE: TER) and JTAG Technologies have jointly demonstrated the ability to test and diagnose advanced digital networks with an integrated boundary-scan solution running on the Teradyne(R) TestStation(TM).
Cerritos, CA, October 28, 2008 – Corelis, Inc. announced today that it will exhibit the latest ScanExpress JTAG/Boundary-scan development and test software as well as Corelis’ ScanExpress JET Functional Emulation Test suite at the upcoming IPC International Test and Inspection Technology Conference in Santa Clara, California, USA.
Sematech Previews Speakers for 3D IC Design And Test Workshop
IC manufacturers, electronic design automation (EDA) professionals and product and test engineers will gather at an upcoming Sematech-sponsored workshop to hear industry leaders address the most pressing design and test issues in 3D and TSV integration.
Synopsys DFT MAX Compression Achieves Mainstream Usage at 90 Nanometers and Below
MOUNTAIN VIEW, Calif., Oct. 28 /PRNewswire-FirstCall/ — Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today announced that Synopsys’ DFT MAX compression product has been successfully deployed at more than one hundred semiconductors companies from all industry segments to substantially reduce the cost of testing digital integrated circuits (ICs).
ATE suppliers join chip makers and OSATs under CAST banner
Several ATE (automated test equipment) companies, IDMs (integrated device manufacturers), and OSAT (outsourced semiconductor assembly and test) companies have formed the “Collaborative Alliance for Semiconductor Test” (CAST), a new industry group that could challenge or complement the well established Semiconductor Test Consortium (STC).
STC Welcomes New Members and Announces Activities at ITC 2008
NIWOT, Colorado, October 27, 2008 — The Semiconductor Test Consortium, Inc. (STC), the leading proponent of the development and adoption of value-added open test standards that benefit the semiconductor industry, today announced that new members Aeroflex Inc., Geotest -Marvin Test Systems, Inc., and National Instruments Corp. have joined to support the Portable Test Instrument Module (PTIM) Working Group efforts, which is part of the Semiconductor Test Interface eXtensions (STIXTM) initiative.
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