Clockless Design - Testable?
Just saw this over at EE Times. Being a DFT engineer for many years, steeped in scan methodology, which is inherently ‘clocky’ ;-), I have to ask: how shall we test these designs?
I haven’t done any research on this yet, but I’m curious. I know we all want less power.
Just wondering…
December 13th, 2006 at 12:49 pm
[...] I’ve heard about this clockless design approach for several years now, and in fact even alluded to it here on this blog recenlty (see “Clockles Design - Testable?“, from Oct 5, 2005). However, until this latest announcement, have heard nothing about how to test it. According tho the complete press release from Handshake Solutions, they have entered into a reciprocal agreement with Mentor Graphics, and one of the outcomes is that designers using Handshake’s Timeless Design Environment (TiDE) can now create ATPG patterns using Mentor’s FastScan. [...]