DFT Digest

I have first-hand knowledge of a growing Southern California (orange county) company in need of a good DFT engineer.  Read the description below, and e-mail me (jford@dftdigest.com) if you’re interested!

DFT Engineer

Needed: A DFT engineer with a wide range of chip making experience. Responsible for planning, impementation and verification of leading-edge design-for-test methodologies in large, high speed  communications devices, including digital methods such as scan/ATPG, test data compression, memory BIST, JTAG, as well as analog DFT measures, to facilitate efficient and high fault coverage manufacturing test and debug.  Also responsible for generation, translation and verification of patterns targeted for ATE.  Participate in ATE test planning, development, correlation and debug. Contribute to the development of overall DFT strategy and infrastructure.

The ideal candidate will have 5+ years of direct DFT experience, with a working knowledge of design-for-test practices, both digital and analog, used on several designs.  Direct experience with ATPG tools (FastScan, TetraMAX or equiv.),  Verilog RTL design and simulation tools, are a must.  Scripting (Perl, TCL, shell) skills are preferable as well.  Familiarity with vector translation tools and flows, and the ATE environment are a plus.

The engineer will be able to thrive in a fast-paced, hard-working environment.  Good written and verbal communication skills are essential.

Candidate must have BSEE/CE/CS at a minimum.