DFT Digest

…well at least the marketing folk do, if not the poor integration team or board test team downstream, trying to test your chip, in-situ.

While I was at ITC, I had the pleasure to meet with Ben Bennetts, who, after perusing DFT Digest noticed a distinct lack of material related to JTAG or boundary scan. It’s true that the material thus far in this blog has been device-level DFT oriented, design-for-test is important at the board level too.

Believe it or not, I had planned to write some discussion fodder for JTAG. Just the basics, and maybe some on the couple of extensions of 1149.1 that I knew about. But during my conversation with Dr. Bennetts, he called my attention to currently on-going activities extending the standards even further to address specific applications of JTAG test: SJTAG and IJTAG.

Without going into too much detail in this one post, SJTAG, which stands for System JTAG, arose from the need to be able to test several boards across backplanes, a common situation in telecom applications, for example. IJTAG, or Internal JTAG is targeted toward the ability to access any of several different types of on-chip test/measurement “instruments”.

The IEEE 1149.1 standard, commonly known as JTAG, has been around since 1990. Since then there has been work on a few extensions: 1149.4 (analog), 1149.5 (module test and maintenance), 1149.6 (advanced digital networks) and 1149.7 (reduced pin count) - who knows what happened to the numbers in between… but it’s clear the concept hasn’t run out of gas.

So in future posts, I’ll try to put together some brief descriptions of JTAG concepts, its applications and extensions. Hopefully, Dr. Bennetts and/or you readers will be kind enough to fill in some of the detail and experiences to make it a truly educational discussion!