Lots going on in the world of JTAG
I mentioned in another post just after ITC 2006, that I’d met Ben Bennetts for the first time. We had breakfast, and talked a bit about this blog I was trying to start up. It was an introductory conversation, but secretly, I was hoping to eventually convince him to work up some material on JTAG for the blog. In the end, I’d like to get plenty of contributed material to appear in this blog. Information from the masters of DFT to the masses. That’s what I’m aiming for!
As for Dr. Bennetts, this being his last year before retiring, he’s pretty busy. But he thought the blog was a good idea, and wanted me to make sure to do plenty on board-level test while I was at it. So far, I’ve failed at that. But eventually, I’d like to do some more reading, and be able to put together something coherent.
He also talked some about how over he years he’s pushed very hard to get board-level tracks included in the ITC program. It seemed that device-level issues dominated the space. He pointed out to me that there is plenty going on with board-level test, and standards are currently being worked on to expand the technology of IEEE 1149.1 to new levels, including both the system level (SJTAG), and at the other end, inside the device (IJTAG).
My new friends over at design-for-test.com have also been recipients of Dr. Bennett’s promotional efforts. They have a whole table of the different JTAG standards activities. Hop on over and see it.
Meanwhile, I have some reading to do…
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