DFT Digest

Magma may have come up with the most unique announcement last month - ATPG that fits inextricably within the Talus implementation tool suite. Not to be outdone, Synopsys came out with a couple of their own.

First was the announcement of low power management for manufacturing test. This effort seems to be a combination of DFT MAX being able to put scan chains together with a minimum of voltage domain crossings (if multiple voltage domains exist in your design), and a new ability of TetraMAX to generate ATPG patterns that fit into a designer’s power budget.

The second announcement introduced TetraMAX’s capability for targeting small delay defects. Most transition delay fault algorithms use the path of least resistance - that is, the easiest path to the next flop, which may have plenty of timing slack, and may never fail the test. If the ATPG were instead looking for the path with the most slack instead, a slow transition on this path is likelier to fail the test. To be able to target the right path obviously requires timing information, which comes from a now built-in PrimeTime interface.

There’s a lot going on here - and if it all works, and is easy enough to use, it looks like Synopsys has a powerful combination. The devil’s always in the details, and the press releases tell you what the tools can do, but not how they do it, or how one can make them do it.

I do have questions - for instance: Is TetraMAX using a programmable fill methodology for power management? And how are the power numbers specified? If TetraMAX is finding the paths with the least slack, are the power management features able to predict possible local IR-drop that may cause false fails, and compensate?

Synopsys also announced a volume diagnostics tool - but I figure there’s another post for that.

’til next time…