Auld Lang Syne
So here it is, New Year’s day. No Rose Parade, no Rose Bowl… what’s a guy to do? Think about DFT? Why not? Today’s a good day to reflect upon what’s been done in the past, and what’s to become of the future. After all, this is the time of the year where the pundits and analysts release their summations of the last year and forecasts for the next year and beyond.
The big stories of last year, according to this article, were DFM (Design-for-Manufacturability) and ESL (English as a Second Language? no, Electronic System Level) tools. The latter deals with the complexity of large electronic systems, whereas the former addresses the complexities of smaller process geometries.
Similarly, DFT methods and technologies need to address these problems: What is test at the system level? And what are the problems of smaller geometries, and what tools are being offered to today’s DFT engineer to help deal with these problems?
What DFT engineers fought for the last two decades to implement in designs (scan, BIST) is now common practice and a bare minimum. But the next few years will see us fighting to implement more rigorous schemes (at-speed scan, test compression, etc.) to keep the escaped defect levels low and keep the device on a reasonably priced ATE. I’d like to explore some of these topics in the coming days and weeks. I think maybe I’d like to start with some discourse on at-speed scan (or delay test, if you prefer).
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