DFT discussion fires up!
Wow - go away for a month and what happens? The readers take over! And that’s a good thing - it’s exactly what I’d like to happen.
For those of you that just look at the front page of DFT Digest, there has been some interesting discussion happening in the comments section of my last post. Goldy, Kiran and Aanand have put some worthwhile discussion on the table (sorry if there was any delay in moderation, since the frequency of comments has been typically low, and I’ve normally been more attentive, it hasn’t been a problem in the past).
To re-cap some of the discussion, Goldy asked about the S rules in Mentor’s DFT Architect, and Aanand was kind enough to elaborate. Aanand asked about scan chain re-ordering, and Kiran responded. Then there was a great discussion question regarding test coverage from Aanand.
I welcome any and all questions here, as well as anyone with help to offer. It’s my goal to keep a free flow of design-for-test information. Unfortunately, sometimes other things bury me, and I don’t get to this as often as I should. I’ll figure out something to minimize that.
Stay tuned…
September 29th, 2007 at 5:00 pm
Hi ,
Can someone elaborate on what is SPEED BINNING ?
Is it something like this ? the chips after manufacturing are tested and sorted based on their max frequency of flawless operation .
September 29th, 2007 at 5:11 pm
Aanand:
You got it exactly. I think it’s used mostly for processor type products, but anywhere you can get more money for faster chips.
JMF
October 1st, 2007 at 5:29 pm
Thanks John.
I got one more question for you ?
In a design functionally we have false paths, means those paths in the design will not be activated at anypoint of time . But why do we dont give that information to the stuck-at ATPG ? . In my experience atleast we normally dont give this information to the ATPG tool during stuck-at but we do when we are making at-speed patterns .
Could you elaborate on this thought to have a deeper understanding ?
- Aanand
October 1st, 2007 at 6:33 pm
Hi Aanand:
False paths are normally defined during synthesis to tell the synthesis tool not to try to hard to optimize them. It doesn’t mean they aren’t activated at all.
An example is a control input to the block which is mainly static during operation - it gets set once, and it’s left that way - you don’t care whether its resolved within a clock period, or more.
That said, since the path still needs to be tested, we don’t tell the ATPG to mask it out during stuck-at. But since it’s not guaranteed to resolve within a clock period, we have to mask it during at-speed.
Make sense?
John
October 1st, 2007 at 7:48 pm
Hello Aanand,
Another example could be of a bus interface/control logic, where you have multiple devices requesting access to the bus, typically there will not be any path from device 1 to another device 2. There will be a path only from Device to the Bus master. But the static timing analyzer sees the path from device1 to device2 via the bus master and so you endup setting FP , else your timing will be a hose. But when you visualize the logic in terms of comb/seq logic, those nodes still needs to be tested for faults else it will impact the operation of the device or device to bus master logic.
Not sure If I could explain clearly . but feel to ask should you have any questions.
October 3rd, 2007 at 11:11 pm
Thanks John and Kiran. I think I got it.