DFT Digest

One of the areas of DFT development pointed out by Richard Quinnell of Test & Measurement World in his article entitled “Vendors pursue DFT strategies“, part of T&M’s DAC roundup, was test for ‘low-power designs’. Another term gaining traction for the process of coming up with these ‘low-power designs’ is ‘Power-Aware Design’. In fact Gabe Moretti is suggesting the use of its acronym, PAD. Fine. Put me on record for for coining the follow-on acronym: PAT. Power-Aware Test. We need more acronyms!

In my mind, there’s actually two facets to this: DFT in the PAD, and PAT. Catch my drift? There’s a difference between being able to actually implement a working test solution in a low-power design and implementing a solution that will yield good results and not burn up the chip.

In the first case (DFT in the PAD), there seems to be a bit of concern for what happens to your DFT effort when some of the latest power reduction techniques are employed. In fact in the article “low-power SOC design takes on new meaning” over at EDN, Ron Wilson worries that techniques such as voltage islands and power gating could complicate, if not be completely incompatible with DFT methodologies. At the least there are additional worries associated with new structures such as level shifters and isolation cells when it comes to testing the PAD.

In the second case, there’s power-aware test (PAT) or DFT - and this is different than the first case. With PAT, the focus is on test methodology and DFT features that will not over-tax the power structures on the device, causing false fails, false passes, and even worse, damaging the chip. Some DFT vendors have worked on creating ATPG vectors with optimized X-fill. Some researchers (see reference 19) have investigated techniques using this capability along with targeting subsets of faults to lower the average switching power during at-speed scan testing.

In either case, there’s quite a bit of interesting work going on in the area. Pay attention…