DFT Digest

OK, settle down, I know there’s gonna be problems. And to be sure, there are many out there that have already begun to encounter them. Oh, yeah, and then there’s 45nm - I just read today that both Intel and IBM have demonstrated 45nm designs. The article linked is pretty fascinating - but a little dis-heartening to those of us who don’t take advantage of Intel’s or IBM’s processes: the magic in the new technology is in the recipe - single atomic layers of Hafnium-based oxide and metal FET gates, resulting in low-leakage/power designs. Neat. But most of us deal with lagging technology from the commercial fabs.

The question is then, what are the biggest hurdles for testability in these ‘commercially available’ smaller geometries? One DFT Digest reader, Kiran asked me to shed some light on this question. My biggest problem with doing that is simple: I haven’t gotten there yet! Professionally, I haven’t gotten any 65nm chips back yet to see where the DFT broke.

After the click, I’ll tell you what I’m worried about, though (not necessarily in the order of importance, but close):

OK - here’s what I’m most worried about with a device in the smaller geometries:

• Test-mode power - With large, fast designs, power is in the forefront of every designer’s mind. And stuck with the commercially available processes, the onus is on the designer to cut power with other techniques, such as clock gating and power-down modes. You know where I’m going here: a full-scan design normally clocks every flip-flop in the design every cycle. And if the power grid on the chip has been designed for ‘mission mode’ (normal operation), you may have a problem in scan mode. In the worst case, you may damage the device. At the very least, if you do have a problem, you will have significant IR-drop in the power grid, causing the device to appear slower. If you’re applying at-speed scan vectors, you may fail good devices. Money down the drain.
• Test Vector Memory - At the very least, in this day and age, we DFT’ers should be pushing for at-speed scan testing. Full-scan stuck-at coverage only is so last century However, ATPG tools generally pump out 3x-5x additional patterns to cover transition faults. So plan on needing that much more ATE scan vector memory, unless you take steps to reduce your data volume. That’s why I’ve elected to use test compression going forward. We’ve discussed test compression several times in this blog.
• Small defects - Small defects are those defects that may cause your design to not work as specified, and yet they are not flagrant enough as to cause a stuck at fault, or even a transition fault. ATPG tools, for all the progress they’ve made, don’t do the best good a job in finding the right defects to target with patterns (the real critical paths). Some of them, however, are starting to leverage STA analysis to create more efficient, bettter patterns. I worry about this, but I haven’t had much experience with it one way or the other (I’ve never done the analysis to know that I had a problem).
• Incoming IP - On the face of it, this is an integration problem: as a Design for Test Engineer, you want to be sure any external IP has all the test hooks you need to have the best overall test solution possible. But the reason I worry more about it at smaller geometries is that the IP designers are fighting the same battles your designers are (in other words, they’re also inexperienced with the new process), and may overlook a test issue - so you need to beware, and offer your guidance.
• Integration w/ Analog circuitry - Once again, this is an integration issue brought on by the tendency to cram more functions into a design when transitioning to a smaller process node. I worry, because I don’t know as much about testing analog blocks as I do digital, and I want to be sure I have the right hooks in place.

That’s off the top of my head - what did I leave out? And how about you? Any of you out there already have experience with 65nm and below? How about sharing your experiences? What took you by surprise? On the other hand, What were you really glad you did plan for?