Test and Verification: Quid Pro Quo
…He said on-chip complexity forced folks to search for better ways to test over the years. Bigger and faster computers had helped, as had testing for stuck-at faults, but the number of transition faults still got bigger. Test engineers beat that stuff back, Rhines said, by shifting to scan-based test, by introducing ATPG, BIST, and ordered-test patterns, and had increased test efficiencies by up to 10x. But it wasn’t enough because even though the cost of components came down, the cost of test did not.
Then in 2001, Rhines said Mentor’s DFT guru Janus Rajski came up with a new approach based on the theory that folks should stop testing what they’ve already tested. Rhines said implementation of the algorithms behind on Rajski’s theory, in combination with test-data compression, has increased test capability 100x and will increase that capability 1000x in the next 5 years. He concluded, “We moved from a mode where we added more cycles of test, to a mode where we added more test per cycle.
Rhines moved on to verification and reiterated what everyone knows – except those who’ve been on a different planet for the least 10 years – verification costs more than design, and that’s way, way too much. [snip - and Rhines says] “I believe that there’s something out there that will do for verification what test-data compression did for test,
So how about that? For so many years, test borrowed from verification, in that functional patterns originally used for verification were re-targeted to the ATE to screen parts. Advances in DFT methodology, from necessity, made huge gains in efficiency by looking at the problem structurally. Now verification, painfully expensive and time consuming, could benefit from the same kind of innovation.
Any ideas out there? There’s money to be made….
March 7th, 2008 at 1:25 pm
> But it wasn’t enough because even though the cost of
> components came down, the cost of test did not.
I was in a dft class several years ago where they presented a
graph from some industry group that plotted the cost of building
a transistor and the cost of testing it over the entire lifespan of the semiconductor industry. It was a log scale and the build cost started in the upper left corner in the 50’s and made a straight line to the lower right. The test cost started in the lower left and was flat.
Crossover was predicted to be around 2010.
Does anyone know who created this graph and if there is an updated one? I think this may have been one of Ben’s classes.
“I believe that there’s something out there that will do for verification what test-data compression did for test”
We used to tell designers that they could do anything that they wanted and we would figure out how to build and test it.
That lasted until the 80’s. We now tell them to design
according to these design_for_synthesis and design_for_test rules and we will figure out how to build and test it.
They need to come up with a set of design_for_verification rules. Chips are getting so big that anything that requires manual intervention will overwhelm your design effort.
John Eaton