DFT Digest

If I had to express the holy grail for testability, it would be “automated coverage”. The most desirable kind of manufacturing test has been automatically generated by tools that leverage design elements and modes to make test time and resource efficient. Of course, I’m talking scan, BIST, and extensions thereof.

But no matter what you do, there will always be the exceptions: analog circuitry, clock generation logic, or custom digital logic, too time-constrained for synthesis, much less scan.

The last one is one I’m thinking about lately. This happens a lot in datapath design, and I’ve run into it a couple of times in my career. One time, I lost a battle with a designer who believed he needed the extra time he could get by using a completely latch-based FIR design. Maybe he did. But what did it mean for me? Loss of automatically driven fault coverage, since we had to make the entire block transparent during scan to get any fault coverage at all. I also got an agreement from the designer that he would come up with enough functional patterns to make our coverage goals. You might already have guessed that I never got those patterns.

SO… the question on my mind today is: In general, what approaches are available and viable enough to get good coverage in a non-scan block (perhaps many stages deep)? What kind of tricks can I play to possibly get an ATPG tool to be able to test such a block - and finish sometime this decade? Am I stuck with functional patterns? Maybe with control/observe points? And is anyone out there actually dong fault-grading anymore?

Let me know…