DFT Digest

Way back in the dark ages, we’d hand craft test patterns for our circuits. We would brainstorm corner cases, and even after we were done, we’d cook up even more patterns to cover odd defects in chips returned from customers. Now, that was living!

Then the logic simulator came to be, and on its heels, the fault simulator. Glory be, we could prove our vectors in the comfort of our own cubicle, and evaluate their effectiveness to boot!

As ICs followed the edict of Moore’s Law (is it just me or does this Moore’s Law appear in 80% of all EDA related articles… still?), the practice of using functional vectors has become but just a facet of the total test solution for best fault coverage. In fact, one hopes that good fault coverage is obtained chiefly with structural test vectors generated by ATPG. Functional vectors are still used mostly to cover speed-related defects. Right? No need to actually fault grade them…

Well, in the real world, most ICs do not consist of 100% scannable sea-of-gates logic. There’s always some custom digital logic, usually too speed or area sensitive for scan. And in some cases, we have large portions or entire chips of this ATPG-unfriendly stuff. These chips must still be tested - so functional patterns or functional BIST (not the commercially available full-scan logic BIST) must serve the objective.

So how do we fault grade them? A friend and fellow DFTer has recently wrestled with this very issue, and offered DFT Digest some insights on the matter. I would like to summarize some of his findings, after the click…

The criteria he mentioned were:

1. Be able to create an aggregate fault coverage number from all of our pattern sets (BIST, SCAN, JTAG, Functional)
2. Have distributed processing
3. Crash recovery
4. Multiple pattern set support

Tools Mentioned - Winterlogic Z10X, Simucad Hyperfault, SynTest TurboFault, Cadence VeriFault, DFTSimulab VDFsim, Mentor FlexTest.

About Z10X:

The Z10X system seems pretty good, but I have never heard of them before… They had transition support which none of the others have. It has distributed processing which will be crucial. I was pretty impressed, and it appears that it can do pretty much what we want - that is get a fault coverage number for [custom] BIST logic, as well as a coverage number for the entire chip after all [the] different pattern sets have been applied. They certainly seem to have a good handle on mixed pattern set fault simulation, and indeed can advise on the most effective patterns and the ones that maybe should be discarded.

About HyperFault:

Hyperfault, I have heard of before although no-one I know has used it… This does not have any transition support, and no scan broad-side-load capability. It does have distributed processing. The underlying simulator for the fault engine is the old Silos simulator which is an interpreted simulator rather than a compiled simulator. This has a huge limitation on block size and speed. They felt the maximum block size would be around the 1-3Mgate range, which is not anywhere near our smallest block. They do not have any top-level fault management tools either, so it would all be hand accounting of the faults which again is a significant drawback.

About TurboFault:

TurboFault. I have seen used this before, along with its sister products. They are very junior class products, and I have not been impressed. The one thing it does have is crash-support (very useful if the [network] dies, and you can restart from where it left off). The other products do not claim this, and this I [view] as essential especially as we are looking at months of fault simulation time (maybe less with distributed processing, but that would mean dedicated machines for a number of weeks).

About VeriFault:

The only other fault simulator I know of and have used is the old Verifault from Cadence. I believe this was shelved many years ago, but we may be able to get a copy. I was reasonably impressed with it, but it was slow slow slow! No distributed processing, as this was not around then (~1998) [editors note: VeriFault did have distributed processing then].

About VDFsim:

Looks like a high school project and I did not even look at them. [editors note: it's true, their website is less than professional, but to be fair, that may not be reflective of the quality of the tool. I personally use tools from a couple off vendors that have never put effort into their website. If anyone out there is using any of the DFTsimulab tools, we'd like to hear from you]

About FlexTest:

I am not sure if Mentor [has] a product or not - never did get a reply out of them. [editors note: Mentor does have a sequential fault simulator, obviously called FlexTest. However, I am sure they have not put a bit of effort into it in years, and it has capacity issues. Don't use it for anything over a few thousand gates.]

To add a couple more notes to this, it may be worth mentioning that Synopsys claims that TetraMAX can be used as a functional fault simulator as well, although I’ve not heard of anyone that’s used them for this specific task, and don’t know whether it’s any good in this regard. My friend talked to Synopsys on it’s capabilities, and they said that the fault sim capabilities were for small blocks only (i.e. small sequential depth).

If any of you out there have fault sim stories and suggestions, please comment!