DFT Digest

Check out the press release here.

I encourage all of you interested in this form of communication to come and participate!

Just a couple of posts ago, I was pointing out that I’d like to be able to attend conference technical sessions in an a-la-carte fashion, since DFT is one of those disciplines that, with a few exceptions, is covered very lightly at many conferences. Why pay full price for just a couple presentations?

One commenter, James Colgan, replied:

“….or how about an Online Trade Show!? No traveling at all!”

I thought, yeah, OK - good idea… and then I was e-surfing this evening and came upon a post over at State of the Media, talking about an online trade show website called Xuropa - apparently run by… wait for it… James Colgan!

Seems like it’s just getting off the ground, but as a vendor you can put marketing material in your online booth, demonstrate products in online labs, and as an individual you can visit these online locations, and network with peers. Check it out…

I sometimes wonder this.

It seems in the past several years, the design-for-test job has grown more complicated (as any other facet of the electronics design discipline), what with new (or more prominent) defect mechanisms and fault models, and new DFT methods and technologies to address them.

I was reading an interview at T&M World with Atun Domic of Synopsys, and the question came up about whether DFT Engineers are necessary to implement the constantly evolving (my words) structures for manufacturing test.  Actually, here’s the exchange:

Q: Is design for test (DFT) strictly the domain of DFT engineers?

A: Certainly, there are DFT specialists, and their responsibility is to construct the DFT strategy for the chip. But verification engineers also need to understand DFT, since they must verify the chip functionality in its test mode. As for design engineers, we see that users of our Design Compiler tool—traditional logic design engineers—also run DFT Compiler and DFT MAX, our scanning and compression tools. We’ve made these tools part of the design flow, so these engineers don’t have to call in test experts.

So DFT engineers can basically sit back and say “let’s do scan!  And JTAG!, Oh, how about some BIST!” And then everyone else will do the implementation and verificaton?  Generate patterns?  How many of you DFT engineers out there have it that easy?

Here’s the thing:  Designers aren’t interested in doing our job.  Verification engineers have enough of a challenge trying to figure out when their job is done.  Again, not interested.

I suppose, as many organizations do, it is possible to plug the DFT gap with people from the design and verification teams, and even the test engineering organization (if one exists).  However, every one of those teams has no better ally than the DFT engineer, because being the multi-disciplinarian he or she is, the DFT engineer understands how trade-offs in testability will affect the test development as well as what impact the DFT implementation may have on the performance of the design, for example.  The good DFTe lives in both the design and test worlds, and can verify the testability as well.  All that and a bag of chips, as they say…

For most of the average joes attending the Design Automation Conference, it’s a time to walk the exhibit floor, witness demos of the latest EDA gear, take in some interesting technical sessions, and maybe attend a party or reception.

But if you dig around the DAC website, you’ll see a link to something called “Collocated Events“. I guess, as is the case with any large conference, the DAC event makes it convenient for other events to happen around the same time and place: various meetings, symposia, even full conferences.

The one link to a collocated event that caught my eye, being a Design for Test guy, is the Global STC Conference, presented by the Semiconductor Test Consortium, taking place just before DAC, June 4-6, in San Diego.

STC is probably most known for promoting the OPENSTAR intiative (open architecture for ATE). They also work on standards for docking interfaces and probe cards, all very test-floor centric activities, not normally the concern of designers. The agenda is dominated by those issues, but on June 5th, the second day of the conference, there are couple of sessions that piqued my interest: “Cooperation Between EDA and ATE: Now More Important Than Ever“, presented by Ed Malloy of Cadence, and “Design for Test - Small Price to Pay on Silicon for High Product Quality“, by Prasad Mantri of Sun.

Hey I have an idea! How about selling conference sessions a la carte? Or in mix-and-match packages (”go to any 10 technical sessions - any conference or symposium of your choice - for only $249!”). Naahh… probably too much travel. But it sounds better sometimes than purchasing a complete conference pass for the 2 or 3 really interesting sessions…

Just a short one - about a month ago, the 2008 Southwest DFT Conference was held in Austin, TX. I blogged about it here. Since I didn’t get to go, I just recently checked back to see if SiliconAid had posted highlights on it’s website - and they’re there, complete with pictures of all the happy DFT’ers and links to some of the presentations. Go check it out! Here’s the link

The conference is held every year by the folks at SiliconAid Solutions, and sponsored by EDA vendors Cadence, Mentor and Synopsys. SiliconAid provides DFT consulting services and offers a family of JTAG-related products.

One more thing: as an update to yesterday’s ‘who’s at DAC’ post, I did miss Virage Logic - they offer DFT solutions for their memories. Also TSSI, the company that created TDS (Test Design System) ATE vector translation software.