Design-With-Test… 2nd sighting
Another article, this by Sanjiv Teneja of Cadence Design Systems, promoting DWT, or “Design-With-Test” has been posted over at Test & Measurement, as a guest commentary. I blogged a few weeks ago about a similar article by another marketing man from the same company. I smell a conspiracy! 
Just kidding, go to DeepChip for conspiracies.
Tomato, tomahto, DFT, DWT - the point is clear: Design-for-Test is not what it used to be. Some of the areas touched on in this article were:
- Power concerns with ATPG and test compression
- Routing congestion concerns with test compression
- Improved defect coverage through timing aware
- Physical awareness during all embedded test (scan, BIST, 1500 core)
I’ve got a couple more - how about:
- Design of AC-JTAG for high-speed differential signals
- Low impact mixed-signal test features
All these issues work to draw the DFT engineer, once upon a time concerned mostly with stuck-at fault coverage and cleverly concocting ATE test modes, deep into the floorplanning, placement, routing and physics of the design flow. You want test compression? Make sure you understand the router’s scan chain re-ordering requirements and limitations. Are your ATPG patterns going to smoke your chip? What happens to your scan chains when your design team decides to use voltage islands?
This is not your daddy’s DFT…
January 14th, 2008 at 10:49 pm
[...] gets more compressed, whether it needs to or not. Cadence decides DFT was not good enough, and trades in ‘F’ for ‘W’, and tester companies start eating each other. DFT Digest joins DFT Forum. And L.T. Wang of SynTest [...]