Design-With-Test?
Very interesting article over at embedded.com, by Tom Jackson of Cadence Design Systems. He makes some excellent points about the necessity of being aware of power consumption throughout the design flow, including the insertion of test structures. But “Design-With-Test”? What he’s describing is what I thought was termed “Power Aware Design and Power Aware DFT”.
So is Mr. Jackson creating a new design discipline? No, maybe just a new term. Maybe it’ll catch on. Regardless, it doesn’t take away from the points he’s trying to make in the article. Some of them I’ve touch on in earlier posts, such as being aware of the effects of all of the flops on your device being toggled at once during ATPG - it may be more activity than ever seen in functional mode. Test compression may exacerbate the problem, and since test compression is designed in ahead of time, ahead of time is when you need to think about it.
But “Design-With-Test”?
February 7th, 2007 at 10:41 pm
[...] has been posted over at Test & Measurement, as a guest commentary. I blogged a few weeks ago about a similar article by another marketing man from the same company. I smell a [...]