DFT in the CBE…
The Cell Broadband Engine, that is. Neat article over at Evaluation Engineering. Written bt DFT engineers from IBM and Brion Keller from Cadence, the article details the overall test approach for this multicore SoC. I don’t know how new the article is, since Cadence released this PR in April of last year. But it was still an interesting read.
With low pin count (128 pins were used for test) as a key goal, they took advantage of the modularity by broadcasting scan to all the Synergistic Processor Elements (SPE) cores at once. In BIST mode they can be tested together or independently.
One of the more interesting bits, I thought, was that for performance and power consumption, much of the data path part of the design was left non-scan. About 40% of the total design turned out to be non-scan, if I read it right. I would classify that as ‘partial-scan’. Anyway, despite the data path being mostly non-scan, they did limit the number of consecutive non-scan stages, enabling them to use ATPG to test it anyway, in sequential mode.
All in all they threw the DFT book at this device, including scan, memory BIST, logic BIST, JTAG and test compression, using Cadence’s OPMISR+ (which should come as no surprise, since that technology was developed at IBM before Cadence bought it).
Impressive job!
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