DFT Digest

November 1, 2007

Is at-speed scan enough? Audience says yes… panel split.

Filed under: At-speed Test, Industry, News, Scan/ATPG — John @ 9:23 pm

The stream of ITC-related press releases has come and gone, and I do plan on discussing more of them, but in between, I’d like to continue to offer some observations of people who were there - something exclusive, that you won’t find anywhere else but DFT Digest.

One such person is Teresa McLaurin, DFT manager at ARM. Teresa is very involved in IEEE activities: She was on the program committee for this years ITC (a topic coordinator for microprocessor test), she was in the working group responsible for creating the IEEE 1500 Core Test standard, and has co-written a book on the subject. Teresa also presented a tutorial at ITC (she and the same people with whom she wrote the book), and presented at the Synopsys SIG event. She was very busy… so I thank her for sharing some of her experience.

Teresa describes the Monday night panel, “At-speed Scan Tests: Reality or Fantasy“:

[It was] a fairly lively panel about whether at-speed scan test can replace functional test. One of the more interesting things that came out of this was that the audience was asked how many thought at-speed structural test could replace functional test, the majority of the audience raised their hands. If this were asked 5 years ago, it probably would have been me and maybe two other people who raised their hands. This may be happening out of necessity. The panel was split on this issue, with Freescale, Intel on one side (functional of course) and TI, LSI Logic and AMD on the other.

I was curious how this panel would go. The title was provocative enough. I thought maybe it meant, “does it exist or not” :-)  Actually I thought that maybe part of the discussion would be a continuation of the logic-BIST vs. at-speed scan debate.

Anyway, it appears that even though for years, EDA vendors have been constantly improving this technology, they haven’t yet convinced everyone. People still like the warm fuzzy  feeling of seeing their device re-verified, at wafer probe, package test, and beyond.  But when you’ve got thousands of man-years invested in your functional patterns, it’s got to be hard to let go.

Leave a Reply