Test Automation for Clockless Design!
I popped up EETimes today to find this item of interest: “Mentor, Handshake partner on clockless IC testing“. I don’t know how y’all feel, and maybe I’m the last one to the party, but I think this is pretty exciting. The designs I’ve worked on for the last few years, at a couple of different places, have pushed the power envelope to the limit.
I’ve heard about this clockless design approach for several years now, and in fact even alluded to it here on this blog recenlty (see “Clockless Design - Testable?“, from Oct 5, 2005). However, until this latest announcement, have heard nothing about how to test it. According tho the complete press release from Handshake Solutions, they have entered into a reciprocal agreement with Mentor Graphics, and one of the outcomes is that designers using Handshake’s Timeless Design Environment (TiDE) can now create ATPG patterns using Mentor’s FastScan.
A fast browse through Handshake’s website shows that they have partnered also with Cadence and Synopsys for the rest of the design flow. They also market low power HT80c51 microcontroller cores and an ARM996HS core that supposedly uses one-third the power of the normal deal. Very interesting. I’m going to look closer, see what other detail I can dig up, and provide an update here.
Cool stuff…
January 21st, 2007 at 1:26 am
I never tied this kind of design.
very good article to read!
January 21st, 2007 at 9:09 pm
Hey Cheelgo:
I don’t think many people have tried this kind of design, and probably won’t until more big companies such as ARM take it up and prove it to be feasible all around.
Thanks for reading, and for the comment!
John