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I suppose this little late-summer/early-autumn heat wave in SoCal makes one want to talk about heat. Makes sense to me – but what’s the excuse for these folks, presumably from the notably cooler Northern California? In the past few days, two different articles were published, one by Chris Allsup and Bill Lloyd of Synopsys, and the other from Anis Uzzaman, Patrick Gallagher, and Edward Malloy, all of Cadence. Both articles addressed the importance of closely considering and taking steps in attempting to put the cap on test-mode power consumption.

The stream of ITC-related press releases has come and gone, and I do plan on discussing more of them, but in between, I’d like to continue to offer some observations of people who were there – something exclusive, that you won’t find anywhere else but DFT Digest.
One such person is Teresa McLaurin, DFT manager at [...]

Tonight there will be all manner of kids, big and small, traipsing through your neighborhood, masquerading as one thing or another. Be kind, or be tricked… Last week, at ITC, I felt a little like a trick-or-treater, walking around dressed up like a real DFT engineer.
Well, yes, I am a DFT engineer, and I [...]

I’ve run across a couple of items in my reading lately about concerns with test-mode power. Not that it’s a new issue, but sometimes when you’re looking for something else, a subject will jump out you a couple of times, causing you to take notice.
Much has been studied and written about test-mode power consumption in [...]

What is ‘delay testing’? Some call it at-speed scan or ATPG. But the bottom line is that this technique involves loading scan data, parallel-clocking it twice (at functional speed – or faster), and shifting the result out of the chip.
First off – there are 2 kinds of delay test: Transition delay test and path [...]