DFT Digest

It’s a full month after DAC has come and gone, so it’s kind of ridiculous to continue.  But I’ve been busy, lazy, on vacation, unmotivated - you pick, what the heck. I think maybe I need to write shorter posts more often, so I have less chance to procrastinate.

As I mentioned in my last post, I did have a couple more conversations with some test-related people.  I reported on Winterlogic last post - but right next to them on the show floor was TSSI.  Now TSSI’s been around a long time, but they’ve been thrrough so many incarnations, it’s like they were money being laundered.  I think I tried to trace their lineage once in a previous post, but bottom line is they’re back to being TSSI anyway.

The main product for TSSI, for years, has been TDS (Test Development Series).  Basically, it’s test vector translation software, but with algorithms built in to analyze event-based input (think VCD) at its core.  It’s modular in design, so it has several ‘readers’ for different simulator output formats, and many ‘writers’ to output vectors for one of many ATE formats.

TSSI introduced a new product at DAC - a tool called ‘FailMap‘ to visually compare ATE results (datalogs, which normally list pattern failures) with the the original simulation output, for easier debugging.  In addition to viewing the failures against the expected response from the simulation, the tool also provides the capability to mask the failures, or ‘learn’ the pattern (change the expected reponse to match actual silicon behavior, and rewrite it, thereby having a passing pattern).

To automate this capability can be a big plus while trying to quickly get patterns going on the tester when silicon first arrives, and real world operation doesn’t exactly match simulation (and face it, these days, with newer processes, it’s not uncommon)  Eventually you have to analyze the failures, but to get a quick initial screen going is tough without a tool like this…

Strolling down the aisle from there, I wandered into the Magma booth and asked about their ATPG tool.  But I’ve already told you that story.  Then I stopped in and chatted with L.T. Wang of SynTest.  Nice man.  I like the books he’s been publishing in the last few years (check out this one, and this one).  He told me he had been very busy, but was going to start writing some papers - to let people know that some of the techniques used for at-speed scan test have been patented (by SynTest).

My next stop was Genesys TestWare.  But this post is already too long.  So until next time…

Just wanted to point to Sramana Mitra’s take on the merger.  One of the last paragraphs in the article brought up an interesting point:

Consolidation is a necessity for the ATE industry just as much as the EDA industry. In fact, a whole new layer of consolidation that bridges the design side and the test side is in order.

[the bolding above is mine]

Then she mentions “inserting ‘testers’ into the chip” (hello! DFT!), and the inevitable declining demand for high end testers, which reminds me of another recent ATE deal that I meant to bring up: Verigy acquires Inovys.  Now that’s fairly old news, but it ties in, because you can see that even the biggest of ‘big iron’ tester companies are investing in the DFT tester space.

My interest was piqued as much as anyone else when I saw the public outing of Cadence’s hostile bid for Mentor last week. But as a DFT guy trying to look objectively at how this might affect other DFT guys/girls, it doesn’t seem like a big deal (although if I listen very carefully, I might hear a collective snicker from the DFT-folk at Freescale, who were shoehorned into Cadence tools a couple of years ago after being a predominantly Mentor house for a long time). So I wasn’t going to even offer my opinion.

But then another deal came to light yesterday that for me, drove home the fact that I work for an industry that seems to be circling the wagons and huddling together to weather an economy that’s taken the wind out of most everybody’s sails. And since this is just on the other side of the DFT fence from EDA, I thought I’d blog it. The deal: a 50/50 merger between Credence and LTX, two ‘big iron’ ATE vendors, both distant trailing competitors in the semiconductor test market that is dominated by the test industry’s ‘big three’: Advantest, Teradyne and Verigy.  The move follows on the heels of Credence’s announcement last week that they sold a $5M piece of their automotive test business to Advantest.  Anything to make a couple bucks…

As in any merger or acquisition, the main reasons given for the merger with LTX are ROI improvements due to combining/slimming certain groups to reduce overhead, and to be able to present themselves as a bigger company supporting more facets of a diverse industry. But just as in the Cadence/Mentor possibility, the interesting speculation is in the product ‘overlap’ (as in the Chris Edwards analysis of ‘Cadentor’), or product ‘rationalization’ as it’s termed by Rick Nelson of T&M World, in this blog post.

The big question is, will it keep them both afloat? The combined value of these two companies (if I read the Yahoo financials correctly) combined will still be ~20% of the smallest of the ‘big three’. And the ATE business is every bit as brutal as EDA… maybe it was a big deal for Cadence to pull out of DAC this year, but most of the ‘big iron’ ATE companies pulled out of ITC some years ago.

Oh yeah, and he new company’s name?  I got nothing. Submissions?

Please…

Two items from the news this past week (presumably timed to coincide with Semicon Japan):

First, it was announced Tuesday that Asset Intertech, who provides boundary scan solutions, acquired Intertest Tech (ITT), an Irish supplier of process emulation technology. This seems to be a cementing of the strategic relationship they’ve had for the past three years, which is targeted toward greater functional coverage using JTAG and CPU emulation for both structural and functional testing of PCBs.

Then, just announced today, Verigy (formerly, Agilent, formerly HP), a ‘big iron’ ATE company, has signed a deal to acquire Inovys, who offers ‘DFT Testers’, such as the Ocelot, Ocelot ZFP and Personal Ocelot. This is an interesting turn of events, given that Advantest (another ‘big iron’ ATE company) recently announced their T2000 tester, which claims to cut the cost of test in half.

My first thought is that it seems that in a tight semiconductor market, the test companies are circling the wagons and working together, a la Asset+ITT and Verigy+Inovys.

My second thought, regarding the IC ATE announcements (in conjunction with other articles that have appeared in the recent past), is that perhaps we’ll be seeing more ATE vendors crawling over toward standards-based systems, after years of resistance. At least with the DFT-class testers - most DFT testers are standards-based testers.

Anybody else have a take on this?