DFT Digest

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Sitting there watching some of the New Years Twilight Zone Marathon, surfing around for ideas – and I landed on an 17-month-old piece written by EDN Editor Ron Wilson on design intent with respect to manufacturing test. The idea was that given increasing operating frequency and design complexity, devices are being “tested as subsystems rather than as conventional components”.

It’s a full month after DAC has come and gone, so it’s kind of ridiculous to continue.  But I’ve been busy, lazy, on vacation, unmotivated – you pick, what the heck. I think maybe I need to [...]

Just wanted to point to Sramana Mitra’s take on the merger.  One of the last paragraphs in the article brought up an interesting point:
Consolidation is a necessity for the ATE industry just as much as the EDA industry. In fact, a whole new layer of consolidation that bridges the design side and the test side [...]

My interest was piqued as much as anyone else when I saw the public outing of Cadence’s hostile bid for Mentor last week. But as a DFT guy trying to look objectively at how this might [...]

Two items from the news this past week (presumably timed to coincide with Semicon Japan):
First, it was announced Tuesday that Asset Intertech, who provides boundary scan solutions, acquired Intertest Tech (ITT), an Irish supplier of process emulation technology. This seems to be a cementing of the strategic relationship they’ve had for the past three years, [...]