DFT Digest

May 2, 2008

Oops, there goes VTS2008

Filed under: Industry, News — John @ 9:47 pm

The week’s gotten away from me and without even a mention of the VLSI Test Symposium (VTS 2008). I’m ashamed… can’t keep up.

VTS was held in Rancho Bernardo, CA (just outside of San Diego), from 4/27 to 5/1. The program looked good. In fact, I’ll go out on a limb and say that for VLSI DFT guy like me, there was as much good content at VTS this year as the most recent ITC (and the tequila cruise to baja didn’t hurt, either). Of course, any one of you out there reading this can rightfully call BS on me, since I attended neither event. Too busy DFT’ing lately.

Anyone out there attend? I’d love to hear your impressions..,

March 10, 2008

DATE 2008 - Starts Today!

Filed under: Industry, News — John @ 11:51 am

Good day DFT folk - just a reminder, DATE 2008 started today. For those of you readers who are lucky enough to be in Munich this week for the event: What are you looking for? What sessions, and/or events do you have your eye on?

One person there this week is JL Gray of Verilab, and author of the blog Cool Verification (there’s a link to his blog in my blogroll over in the right-hand sidebar). You can see his initial post regarding this year’s DATE here.

JL solicited suggestions for interesting session or events from his verification readers. I had to chime in from the perspective of a test guy. Here’s what I said:

For Tuesday, First, I’d go to session 1.5, Advances in BIST for mixed-signal devices, and see if I could make it through all the math without a brain implosion. It’s an area of test that needs attention.

Then I’d stagger over to session 2.5, Advances in SoC Test, where I’d be a bit more comfortable, because that’s where I live - very concerned about test data volume.

Wednesday, I’d attend Session 6.5, the Hot Topic: Test Challenges for Low Power Devices. I think this is the top test issue for 2008.

Beyond that, I’m pretty interested in any of the musings surrounding the next couple of technology nodes (45nm, 22nm). I’ll be living through them in the next couple of years. Exciting times… the variability dimension in chip design is a new frontier, I think.

Low-power test design is also a big interest for me - so any of those papers would attract my attention.

So what do you all think? What interests you? Again, if any of you are in attendance, I’d really appreciate an update from you.

Bis Später!!