DFT Digest

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Something interesting happened today. Well, interesting to me. After all, I’m a DFT guy. Anyway, I’m waiting for an ATPG run to crash (and I know it will crash, because I just threw the scripts together – it’s a Murphy’s Law thing, I’m sure). So what does the typically efficient person do when waiting in front of a computer? Right – I’m browsing the internet.

It is my sworn duty as a design-for-test blogger to bring you information relating to DFT wherever I may find it. Today, I must point you to an excellent series of posts over at The Digital Electronics Blog, on the subject of the economics of test, written by Joachim Bauer, a test engineer from France. Click here to read more…

I spent the morning taking advantage of proximity to vendors to solve a couple of problems, so the first presentation I saw today was the invited address given by AMD Fellow Jeff Rearick: This Is a Test: How to Tell if DFT and Test Are Adding Value to Your Company. I thought it was a very interesting address, so let’s see if I can relay some of what was said:

Two items from the news this past week (presumably timed to coincide with Semicon Japan):
First, it was announced Tuesday that Asset Intertech, who provides boundary scan solutions, acquired Intertest Tech (ITT), an Irish supplier of process emulation technology. This seems to be a cementing of the strategic relationship they’ve had for the past three years, [...]

Pssst!! Want to boost your profit margins by a few percent? Here’s the secret: take your test to the design (you know… DFT!). This is the message of a commentary by Jim Healy, CEO of LogicVision.
“Manufacturing should have the ability to drive test cost and final package yield criteria into design specs…”
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