DFT Digest

Update: I could swear I published this article with a title, but then I noticed it coming up blank in my feed…

All along I’ve said that DAC’s not really my show, but it was more interesting this year, given the whole EDA Bloggers Birds of Feather deal. It inspired some good discussion, and I hope it becomes a repeated occurrence as we, the independent bloggers establish our value in the EDA community.

However, as I mentioned in a previous post, in my short walk about the floor, besides noting the distinct lack of ATPG in the Magma booth, I did have a couple of enjoyable conversations with some test-related exhibitors.

First, I talked to the guys in the WinterLogic booth. This was the first year at DAC for WinterLogic. Not quite a ‘household’ name in DFT circles, this company markets a product called Z01X, which is a “high-speed functional fault simulator for Verilog designs.”   Now, obtaining coverage by fault simulation, as a matter of practice for functional vectors, has taken a back seat in recent years to to the coverage achieved with structural methods (scan and BIST). But structural fault coverage is never a complete solution for the contemporary SoC, so the structural test-suite almost always has to be augmented with functional patterns.

Now the last time I actually used a fault simulator, nobody was talking about transition delay faults or bridge faults, but current fault simulators (I’ll go out on a limb here and say there are two: SynTest’s TurboFault and Z01X) cover both those classes of faults, and claim performance improvements and other added capabilities over previous generations of fault grading software.

One of the ways in which the folks at WinterLogic do believe they are unique is in their “test ordering and redundant test elimination capabilities“.  Z01X performs testability analysis on the design with respect to each test, then starting with the best coverage test, ranks and reorders the remaining tests after each run.  They claim to be able to reduce the overall test-set by as much as 50%.

This job of test optimization is many times tackled by the test or product engineer after a device has been in production to optimize test time. The decision to reorder or eliminate tests is based upon the statistics of how often particular tests catch defective parts, determined over time by testing many devices.  I’m sure a priori test selection in the pre-silicon domain by relative fault coverage is practiced also, in an ad hoc fashion, but Z01X would be the first productization of this as applied to functional pattern sets (ATPG tools also have this capability built-in, for structural patterns).

The folks in the Winterlogic DAC booth claimed to have produced excellent results with some very big customers with this technology.  After talking with them, I shuffled to the right (to the next booth) where TSSI was set up.  I’ll talk more about that in my next post, as well as my conversations with SynTest, Genesys TestWare, and LogicVision.

Stay tuned…

I just got back from DAC, and the ‘Birds of a Feather’ EDA bloggers session. I’ve got to say, it felt a little more like a bunch of dogs getting to know each other. Seems to me that independent EDA bloggers just had their collective butts sniffed by journalists and PR/marketing folk. Well, mission accomplished, I guess. We’re all blogging for different reasons, and thanks to Peggy for pointing out that it’s a freedom of speech thing and that’s what makes it interesting.

First off, for me - well I’ve said it before, DAC is not really my show, mostly because test and DFT are not very well represented. But I showed up about mid-afternoon and talked with some of the test-related vendors, such as WinterLogic, TSSI, SynTest, Genesys and LogicVision. More on those conversations in another post.

I was traveling light, so no laptop. I had also neglected to re-check the location of the BoF session and wandered around for a few minutes searching, before recognizing Richard Goering and asking directions (irony alert: blogger asks journalist for directions to a blogging event - I know, right?).

I walked in as David Lin of Denali was being harassed mid-way through his presentation on corporate blogging. There was an animated discussion trying to triangulate the definition of blogging. Are you really a blogger if you’re just publishing white-papers for your company? Isn’t a blog just the modern day equivalent of a ‘column’? Of course there was the predictable exchange between the journalist and the corporate marketer about the current plight of the EDA press.

A fairly good mix of folks showed up (there seemed to be 30-40 people all-in-all, you’d have to ask JL what his count was). John Blyler and a couple other journalist-bloggers from Chip Design magazine were there, as well as Richard Goering, and Peggy Aycinena, all except Goering professing to be bloggers in their own way. Also in attendance seemed to be several marketing/PR people, there to figure out how communicate with bloggers - I hadn’t realized we were that hard to contact - but I think the real question was “how can I use you as another channel to my customers?” There was also Janick Bergeron of Verification Guild - and the aptly dubbed “Original EDA blogger”, John Cooley, was also there. My only complaint is that the “independent” EDA blogger was somewhat under-represented.

After another short talk by Steve Liebson, the attendees took some time to introduce themselves and their interest in EDA blogging. Then JL attempted to open he floor to some different topics for discussion - when a curious thing happened: He asked me what I thought of publishing solicited content, and as I answered - no lie - half the room suddenly stood up and left. What is something I said, or… ? It was quite comical, really. But I’m a good sport, so I checked my arm-pits and continued.

Anyway, aside from the fact that most of the conversation seemed to center around the blog as a marketing tool, it was all good. I’d like to thank JL, Harry, Sean and David for putting together a fascinating event!

For most of the average joes attending the Design Automation Conference, it’s a time to walk the exhibit floor, witness demos of the latest EDA gear, take in some interesting technical sessions, and maybe attend a party or reception.

But if you dig around the DAC website, you’ll see a link to something called “Collocated Events“. I guess, as is the case with any large conference, the DAC event makes it convenient for other events to happen around the same time and place: various meetings, symposia, even full conferences.

The one link to a collocated event that caught my eye, being a Design for Test guy, is the Global STC Conference, presented by the Semiconductor Test Consortium, taking place just before DAC, June 4-6, in San Diego.

STC is probably most known for promoting the OPENSTAR intiative (open architecture for ATE). They also work on standards for docking interfaces and probe cards, all very test-floor centric activities, not normally the concern of designers. The agenda is dominated by those issues, but on June 5th, the second day of the conference, there are couple of sessions that piqued my interest: “Cooperation Between EDA and ATE: Now More Important Than Ever“, presented by Ed Malloy of Cadence, and “Design for Test - Small Price to Pay on Silicon for High Product Quality“, by Prasad Mantri of Sun.

Hey I have an idea! How about selling conference sessions a la carte? Or in mix-and-match packages (”go to any 10 technical sessions - any conference or symposium of your choice - for only $249!”). Naahh… probably too much travel. But it sounds better sometimes than purchasing a complete conference pass for the 2 or 3 really interesting sessions…

Just a short one - about a month ago, the 2008 Southwest DFT Conference was held in Austin, TX. I blogged about it here. Since I didn’t get to go, I just recently checked back to see if SiliconAid had posted highlights on it’s website - and they’re there, complete with pictures of all the happy DFT’ers and links to some of the presentations. Go check it out! Here’s the link

The conference is held every year by the folks at SiliconAid Solutions, and sponsored by EDA vendors Cadence, Mentor and Synopsys. SiliconAid provides DFT consulting services and offers a family of JTAG-related products.

One more thing: as an update to yesterday’s ‘who’s at DAC’ post, I did miss Virage Logic - they offer DFT solutions for their memories. Also TSSI, the company that created TDS (Test Design System) ATE vector translation software.

This week, I’ll try to pass along Design-for-Test related DAC news as it comes along…

First, it was announced today that the standards organization Accellera has selected Bruce Cory, a DFT manager at NVIDIA, to receive the 5th annual Technical Excellence Award, for leading the effort to bring the Open Compression Interface (OCI) to be approved by the Accellera membership, and continuing the effort to pass it as an IEEE standard (IEEE 1450.6.1, which I guess is an extension to the CTL standard).

The OCI standard will be an important step in establishing tool independence with regard to test data compression and diagnosis, while still protecting EDA vendor’s compression IP. Currently, once test compression IP from a certain vendor is incorporated into a design, ATPG tools from the same company must be used, as well as any other tool down the line (yield analysis, for example) that hopes to use ATPG data. This can get particularly problematic, especially in manufacturing and test environments that would have to support as many tool flows as there are test compression schemes.

Also today,  LogicVision announced the Dragonfly Test Platform, which will be demonstrated at DAC.  The new tool seems to be  an integration of existing, and in some cases improved versions of LogicVision’s embedded test tools addressing memory BIST and logic BIST, as well as debug and analysis tools such as Silicon Insight and Yield insight.

Earlier this month Genesys Testware announced announced yet another Design-for-X tool: Design-for-Leakage-Test (DFLT).  This is actually a feature added to their Hierarchical DFT tool, HiertestMaker, and addresses problems due to lack of testability around power-aware design structures, such as “power switches, and isolations gates”, and I assume level-shifters.  Here’s the press release.  Someone over at Genesys needs to work on their website: you may notice if you go to their homepage, the latest news is from ITC 2006, and the upcoming event is DAC 2007

Winterlogic, maker of the fault simulation tool Z01X will be exhibiting at DAC for the first time.

SynTest will also be exhibiting - stop by and congratulate L.T. Wang for being elected IEEE fellow earlier this year

Nothing test-related for Synopsys, and this is not necessarily DAC-related, but I have to brag that Synopsys has added a link to this blog on their Galaxy DFT page.  Mentor, Cadence?   Hello?