DFT Digest

Update: I could swear I published this article with a title, but then I noticed it coming up blank in my feed…

All along I’ve said that DAC’s not really my show, but it was more interesting this year, given the whole EDA Bloggers Birds of Feather deal. It inspired some good discussion, and I hope it becomes a repeated occurrence as we, the independent bloggers establish our value in the EDA community.

However, as I mentioned in a previous post, in my short walk about the floor, besides noting the distinct lack of ATPG in the Magma booth, I did have a couple of enjoyable conversations with some test-related exhibitors.

First, I talked to the guys in the WinterLogic booth. This was the first year at DAC for WinterLogic. Not quite a ‘household’ name in DFT circles, this company markets a product called Z01X, which is a “high-speed functional fault simulator for Verilog designs.”   Now, obtaining coverage by fault simulation, as a matter of practice for functional vectors, has taken a back seat in recent years to to the coverage achieved with structural methods (scan and BIST). But structural fault coverage is never a complete solution for the contemporary SoC, so the structural test-suite almost always has to be augmented with functional patterns.

Now the last time I actually used a fault simulator, nobody was talking about transition delay faults or bridge faults, but current fault simulators (I’ll go out on a limb here and say there are two: SynTest’s TurboFault and Z01X) cover both those classes of faults, and claim performance improvements and other added capabilities over previous generations of fault grading software.

One of the ways in which the folks at WinterLogic do believe they are unique is in their “test ordering and redundant test elimination capabilities“.  Z01X performs testability analysis on the design with respect to each test, then starting with the best coverage test, ranks and reorders the remaining tests after each run.  They claim to be able to reduce the overall test-set by as much as 50%.

This job of test optimization is many times tackled by the test or product engineer after a device has been in production to optimize test time. The decision to reorder or eliminate tests is based upon the statistics of how often particular tests catch defective parts, determined over time by testing many devices.  I’m sure a priori test selection in the pre-silicon domain by relative fault coverage is practiced also, in an ad hoc fashion, but Z01X would be the first productization of this as applied to functional pattern sets (ATPG tools also have this capability built-in, for structural patterns).

The folks in the Winterlogic DAC booth claimed to have produced excellent results with some very big customers with this technology.  After talking with them, I shuffled to the right (to the next booth) where TSSI was set up.  I’ll talk more about that in my next post, as well as my conversations with SynTest, Genesys TestWare, and LogicVision.

Stay tuned…

Just wanted to point to Sramana Mitra’s take on the merger.  One of the last paragraphs in the article brought up an interesting point:

Consolidation is a necessity for the ATE industry just as much as the EDA industry. In fact, a whole new layer of consolidation that bridges the design side and the test side is in order.

[the bolding above is mine]

Then she mentions “inserting ‘testers’ into the chip” (hello! DFT!), and the inevitable declining demand for high end testers, which reminds me of another recent ATE deal that I meant to bring up: Verigy acquires Inovys.  Now that’s fairly old news, but it ties in, because you can see that even the biggest of ‘big iron’ tester companies are investing in the DFT tester space.

I sometimes wonder this.

It seems in the past several years, the design-for-test job has grown more complicated (as any other facet of the electronics design discipline), what with new (or more prominent) defect mechanisms and fault models, and new DFT methods and technologies to address them.

I was reading an interview at T&M World with Atun Domic of Synopsys, and the question came up about whether DFT Engineers are necessary to implement the constantly evolving (my words) structures for manufacturing test.  Actually, here’s the exchange:

Q: Is design for test (DFT) strictly the domain of DFT engineers?

A: Certainly, there are DFT specialists, and their responsibility is to construct the DFT strategy for the chip. But verification engineers also need to understand DFT, since they must verify the chip functionality in its test mode. As for design engineers, we see that users of our Design Compiler tool—traditional logic design engineers—also run DFT Compiler and DFT MAX, our scanning and compression tools. We’ve made these tools part of the design flow, so these engineers don’t have to call in test experts.

So DFT engineers can basically sit back and say “let’s do scan!  And JTAG!, Oh, how about some BIST!” And then everyone else will do the implementation and verificaton?  Generate patterns?  How many of you DFT engineers out there have it that easy?

Here’s the thing:  Designers aren’t interested in doing our job.  Verification engineers have enough of a challenge trying to figure out when their job is done.  Again, not interested.

I suppose, as many organizations do, it is possible to plug the DFT gap with people from the design and verification teams, and even the test engineering organization (if one exists).  However, every one of those teams has no better ally than the DFT engineer, because being the multi-disciplinarian he or she is, the DFT engineer understands how trade-offs in testability will affect the test development as well as what impact the DFT implementation may have on the performance of the design, for example.  The good DFTe lives in both the design and test worlds, and can verify the testability as well.  All that and a bag of chips, as they say…

This week, I’ll try to pass along Design-for-Test related DAC news as it comes along…

First, it was announced today that the standards organization Accellera has selected Bruce Cory, a DFT manager at NVIDIA, to receive the 5th annual Technical Excellence Award, for leading the effort to bring the Open Compression Interface (OCI) to be approved by the Accellera membership, and continuing the effort to pass it as an IEEE standard (IEEE 1450.6.1, which I guess is an extension to the CTL standard).

The OCI standard will be an important step in establishing tool independence with regard to test data compression and diagnosis, while still protecting EDA vendor’s compression IP. Currently, once test compression IP from a certain vendor is incorporated into a design, ATPG tools from the same company must be used, as well as any other tool down the line (yield analysis, for example) that hopes to use ATPG data. This can get particularly problematic, especially in manufacturing and test environments that would have to support as many tool flows as there are test compression schemes.

Also today,  LogicVision announced the Dragonfly Test Platform, which will be demonstrated at DAC.  The new tool seems to be  an integration of existing, and in some cases improved versions of LogicVision’s embedded test tools addressing memory BIST and logic BIST, as well as debug and analysis tools such as Silicon Insight and Yield insight.

Earlier this month Genesys Testware announced announced yet another Design-for-X tool: Design-for-Leakage-Test (DFLT).  This is actually a feature added to their Hierarchical DFT tool, HiertestMaker, and addresses problems due to lack of testability around power-aware design structures, such as “power switches, and isolations gates”, and I assume level-shifters.  Here’s the press release.  Someone over at Genesys needs to work on their website: you may notice if you go to their homepage, the latest news is from ITC 2006, and the upcoming event is DAC 2007

Winterlogic, maker of the fault simulation tool Z01X will be exhibiting at DAC for the first time.

SynTest will also be exhibiting - stop by and congratulate L.T. Wang for being elected IEEE fellow earlier this year

Nothing test-related for Synopsys, and this is not necessarily DAC-related, but I have to brag that Synopsys has added a link to this blog on their Galaxy DFT page.  Mentor, Cadence?   Hello? 

In the past there have been requests to address analog/Mixed-signal Design for Test on this blog.  I’ve tried to incite discussion on the subject a couple of times in previous posts (here and here) - limp efforts, at best. To be honest, I wasn’t able to come up with much beyond the mantra of all DFT engineers: maximize controllability and observability.  But that doesn’t mean there wasn’t plenty going on - just that I wasn’t paying attention.  Well, sort of.

At least one commenter to my posts dredged up the name Opmaxx; It’s the name of a company founded in the mid/late 90’s to create products for analog and mixed-signal ‘design centering’ and test automation.  I remember it because it came about just as I was getting more involved in DFT and starting to pay attention to the industry.  One of the products introduced by Opmaxx was called BISTMaxx; it inserted structures that subdivided any circuit into blocks that were then isolated during test mode and turned into oscillators.  The underlying concept is that faulty circuits would produce different oscillation frequencies than good circuits.  The general term for this method is called oscillation BIST.

I know of at least one instance (takes you to an article - scroll down to ‘Test Challenges’) where someone put this into their chips and into production.  Opmaxx was acquired by Fluence, then a subsidiary of Credence, was later absorbed into another Credence acquisition called IMS.  At one point, I believe they were selling BIST products for DACs, ADCs, VCOs and PLLs.  Eventually, at a time I’m unable to pinpoint, Credence dropped these products.  The industry was either not ready or unwilling to accept them, I guess.

However, still in the MS-DFT game was, and is, LogicVision.  I don’t know if they ever had ADC/DAC BIST, although Stephen Sunter (director of mixed-signal and parametric test at LogicVision) has presented papers regarding algorithms for implementing it.  They have had, and still do have A PLL BIST solution, and recently they have developed a SerDes BIST solution, based on undersampling, that claims to achieve sub-picosecond accuracy on any tester.  The SerDes BIST is based upon looping transmit data back through the receive channel, while varying certain parameters - thus being able to actually characterize the ‘eye’ of the signal… (more…)