DFT Digest

Just wanted to point to Sramana Mitra’s take on the merger.  One of the last paragraphs in the article brought up an interesting point:

Consolidation is a necessity for the ATE industry just as much as the EDA industry. In fact, a whole new layer of consolidation that bridges the design side and the test side is in order.

[the bolding above is mine]

Then she mentions “inserting ‘testers’ into the chip” (hello! DFT!), and the inevitable declining demand for high end testers, which reminds me of another recent ATE deal that I meant to bring up: Verigy acquires Inovys.  Now that’s fairly old news, but it ties in, because you can see that even the biggest of ‘big iron’ tester companies are investing in the DFT tester space.

I just got back from DAC, and the ‘Birds of a Feather’ EDA bloggers session. I’ve got to say, it felt a little more like a bunch of dogs getting to know each other. Seems to me that independent EDA bloggers just had their collective butts sniffed by journalists and PR/marketing folk. Well, mission accomplished, I guess. We’re all blogging for different reasons, and thanks to Peggy for pointing out that it’s a freedom of speech thing and that’s what makes it interesting.

First off, for me - well I’ve said it before, DAC is not really my show, mostly because test and DFT are not very well represented. But I showed up about mid-afternoon and talked with some of the test-related vendors, such as WinterLogic, TSSI, SynTest, Genesys and LogicVision. More on those conversations in another post.

I was traveling light, so no laptop. I had also neglected to re-check the location of the BoF session and wandered around for a few minutes searching, before recognizing Richard Goering and asking directions (irony alert: blogger asks journalist for directions to a blogging event - I know, right?).

I walked in as David Lin of Denali was being harassed mid-way through his presentation on corporate blogging. There was an animated discussion trying to triangulate the definition of blogging. Are you really a blogger if you’re just publishing white-papers for your company? Isn’t a blog just the modern day equivalent of a ‘column’? Of course there was the predictable exchange between the journalist and the corporate marketer about the current plight of the EDA press.

A fairly good mix of folks showed up (there seemed to be 30-40 people all-in-all, you’d have to ask JL what his count was). John Blyler and a couple other journalist-bloggers from Chip Design magazine were there, as well as Richard Goering, and Peggy Aycinena, all except Goering professing to be bloggers in their own way. Also in attendance seemed to be several marketing/PR people, there to figure out how communicate with bloggers - I hadn’t realized we were that hard to contact - but I think the real question was “how can I use you as another channel to my customers?” There was also Janick Bergeron of Verification Guild - and the aptly dubbed “Original EDA blogger”, John Cooley, was also there. My only complaint is that the “independent” EDA blogger was somewhat under-represented.

After another short talk by Steve Liebson, the attendees took some time to introduce themselves and their interest in EDA blogging. Then JL attempted to open he floor to some different topics for discussion - when a curious thing happened: He asked me what I thought of publishing solicited content, and as I answered - no lie - half the room suddenly stood up and left. What is something I said, or… ? It was quite comical, really. But I’m a good sport, so I checked my arm-pits and continued.

Anyway, aside from the fact that most of the conversation seemed to center around the blog as a marketing tool, it was all good. I’d like to thank JL, Harry, Sean and David for putting together a fascinating event!

For most of the average joes attending the Design Automation Conference, it’s a time to walk the exhibit floor, witness demos of the latest EDA gear, take in some interesting technical sessions, and maybe attend a party or reception.

But if you dig around the DAC website, you’ll see a link to something called “Collocated Events“. I guess, as is the case with any large conference, the DAC event makes it convenient for other events to happen around the same time and place: various meetings, symposia, even full conferences.

The one link to a collocated event that caught my eye, being a Design for Test guy, is the Global STC Conference, presented by the Semiconductor Test Consortium, taking place just before DAC, June 4-6, in San Diego.

STC is probably most known for promoting the OPENSTAR intiative (open architecture for ATE). They also work on standards for docking interfaces and probe cards, all very test-floor centric activities, not normally the concern of designers. The agenda is dominated by those issues, but on June 5th, the second day of the conference, there are couple of sessions that piqued my interest: “Cooperation Between EDA and ATE: Now More Important Than Ever“, presented by Ed Malloy of Cadence, and “Design for Test - Small Price to Pay on Silicon for High Product Quality“, by Prasad Mantri of Sun.

Hey I have an idea! How about selling conference sessions a la carte? Or in mix-and-match packages (”go to any 10 technical sessions - any conference or symposium of your choice - for only $249!”). Naahh… probably too much travel. But it sounds better sometimes than purchasing a complete conference pass for the 2 or 3 really interesting sessions…

The Design Automation Conference is just around the corner. DAC’s not usually a conference that commands much interest with regard to DFT… I recently wrote a blog post complaining of that fact, but never posted it (I like to let posts like that simmer for awhile, and many times, a re-reading of them will expose them as pathetic/worthless, and they never hit the internet). ITC is really the place for our kind of fare.

However, as long as DAC is local enough (for me, that’s Anaheim or San Diego), I like to go for the free day, skulk about the booths for anything interesting, collect schwag, try to run into as many old acquaintances as possible, and maybe meet someone new.

This year, there’s something different that may or may not happen, but the fact that it’s actually being considered is a sign of the times: a “Birds of a Feather” session featuring EDA bloggers. It’s being organized chiefly by JL Gray of Cool Verification, who really has the most traction as an EDA blogger - along with a few others that have been willing to help out. If 10 bloggers commit to showing up, a room can be reserved, and a discussion will take place. If not, the few who’ve committed can go “grab a beer and have some ad hoc discussions”. Either option is good with me. But exposing the online community to the greater EDA industry can only be a good thing in my eyes, so I’m encouraging anyone out there who has interest in participating to speak up and show up.

Here’s to making new acquaintances this year at DAC…

Last week, John Cooley published the results of his 2008 DeepChip Synopsys Survey, and of course I went straight to item #6, entitled “Synopsys DFT Compiler/TetraMAX vs. Mentor DFT Advisor/FastScan“. There are some surprises and head scratchers:

• By John’s count, Synopsys DFT Compiler only has 50% of the scan insertion market. Gary Smith believes it’s more like 78%.
• According to his respondents, Synopsys TetraMAX is used twice as much as Mentor FastScan! Gary Smith’s numbers say the exact opposite.

Even John wonders, “…according to Gary, my DFT Compiler percentage is too low and my TetraMAX percentage is too high. Why that is, I don’t know“.

Well, a couple things occurred to me:

First, I believe John’s audience (and by extention, survey respondents) is skewed in a couple of ways:

• It’s ESNUG (The S stands for Synopsys), so mostly Synopsys users responded.
• It’s my belief that the Deep Chip audience are mostly designers, who are famous for not knowing exactly what’s going on in the DFT world, even on their own chips.

Second, related to my characterization of chip designers’ ignorance of their own DFT methodology, is that many don’t realize that the tools don’t stack up one for one - in other words, If I use Synopsys DFT MAX (compression tool) and Synopsys TetraMAX (ATPG tool), it’s not the same as using Mentor TestKompress (compression tool) and Mentor FastScan (ATPG tool). That’s because FastScan comes as a part of TestKompress. The Synopsys tools are separate. So when someone reports using TestKompress, you must put a mark in both The TestKompress and FastScan columns in order to make an apples-to-apples comparison.

So what do I think? Well, I believe Gary Smith’s DFT Compiler number. I think fewer and fewer people are inserting scan after synthesis is complete, most now compile scan-ready as part of their synthesis flow. Scan stitching can be done also with the place & route tool in some cases. So about 80% seems right.

On the other hand, I don’t believe either Gary or John about the ATPG tool balance. I think it’s closer than either of them say, but with TetraMAX slightly in the lead.  There are many decision makers out there today putting together cost-driven tool bundles - and will go Synopsys because they’ve got the whole flow integrated.

I have no hard data to support any of my claims, but it’s the sense I get when I talk to people…