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[editors note: This post is third in a regular series of featured contributions from Stephen Pateras of LogicVision]

Probably one of the hottest design topics these days is power minimization. This is not surprising given how much we love our high-performance mobile and wireless toys. But what does that mean to BIST solutions?

[editors note: This post is third in a regular series of featured contributions from Stephen Pateras of LogicVision]

John provided a good overview of embedded memory repair techniques in his Memory Repair Basics post late last year. Although there’s been some limited adoption of memory repair at 90nm, at 65 and 45nm it’s a whole different story. In fact, at 45nm, it’s becoming the norm. But, like any new product, there’s a fair amount of uncertainty about when to use memory repair and how much is too much. (Yes, you can have too much of a good thing). Let’s see if I can clear up some of the confusion with a few (hopefully) helpful tips.

How do you repair a memory? You don’t, once brain cells are dead, they’re dead – right? No problem, we all use only about 10% of our brains, so there’s plenty left to work with – 90% redundancy!

OK, well that 10% story is a huge myth, but having extrabrain cells to work with is a decent analogy for how we attempt to improve yields during the test of embedded memories. Click here to read more…