DFT Digest

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Remember in my last post, where I told you how weird it was to suddenly be seeing all these references to 3D ID design technology? Well it didn’t stop. Literally, the day I posted that entry, I got the new issue of IEEE Design & Test – a special issue on, you guessed it: 3D IC Design and Test.

The same day, I was cleaning my desk, and found a couple of papers that I had printed out a couple of months ago and forgot about, from DATE ‘09. One was entitled Test Architecture and Optimization for Three-Dimensional SoC’s.

Sometimes a post just begs to be written. Subconsciously, little reminders crop up in your input stream (a.k.a. eyes and ears) that prod you into doing something. Last week, like a Hitchcock blonde, it seemed like every time I turned around, something referring to 3-D technology popped out at me. I think it started when I began searching for material on JTAG implementations for MCMs…

Need to catch up on a few things… with the onset of the DAC season, there are always some interesting things that pop up, even if the conference is light on test. Here is a small list of items that have passed into my weary view, in no particular order:

image: Al Souza, Potpourri Redux, 2007