DFT Digest

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As I was putting together a post with some recent DFT-related news, I came across a couple of links referencing recent work on an extension to the IEEE 1149.1 (a.k.a. JTAG). As I read about this impending standard, my interest was piqued, so I embarked on a hyper-google for “IEEE 1149.7″, and came to realize I had only experienced the tip of an iceberg of press releases and product announcements - all from this month!

A bit of catch-up here - a potpourri of news and press-releases from the last two weeks:

International Test Conference - The Cornerstone of Test Week(TM) - Hosts 39th Conference in Santa Clara, California, October 28 - 30, 2008

“International Test Conference, the highlight of the annual Test Week(TM) activities and the leading forum for electronics test technology, promises to engage and stimulate attendees from the test and design community with its technical program and activities when the doors open at the 39th annual ITC.”

Let me hear you say yeah!

Karen Bartleson over at her blog, The Standards Game, issued an invitation to all who care*, to become a part of the balloting process for the IEEE P1450.6.1, “Standard for Describing On-Chip Scan Compression”, or Open Compression Interface. Karen has a short explanation of the idea behind the standard, and I’ve blogged about it here before. It was ratified by Accellera in October of 2006.

System Verilog was signed off as a standard by IEEE in late 2005. In the 2-1/2 years since, front-end design tools for synthesis and verification have been making significant strides in support of the standard - not without limitations and missteps - but the effort is there. Progress has been made. So [...]