DFT Digest

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Remember in my last post, where I told you how weird it was to suddenly be seeing all these references to 3D ID design technology? Well it didn’t stop. Literally, the day I posted that entry, I got the new issue of IEEE Design & Test – a special issue on, you guessed it: 3D IC Design and Test.

The same day, I was cleaning my desk, and found a couple of papers that I had printed out a couple of months ago and forgot about, from DATE ‘09. One was entitled Test Architecture and Optimization for Three-Dimensional SoC’s.

Sometimes a post just begs to be written. Subconsciously, little reminders crop up in your input stream (a.k.a. eyes and ears) that prod you into doing something. Last week, like a Hitchcock blonde, it seemed like every time I turned around, something referring to 3-D technology popped out at me. I think it started when I began searching for material on JTAG implementations for MCMs…

About once a month, Mentor publishes a little piece on their website called Test Talk, written by Al Crouch. This month’s edition, entitled ‘Outsourcing, the Scrabble Method’, is a Dilbertian look at outsourcing, and of course, has its DFT-related tie-in: weighted fault coverage and n-detect. Hmmm… what could weighted fault coverage and outsourcing [...]

Today I received an e-mail from Dr. Ben Bennetts, DFT Consultant (Semi-retired) with a great introduction to some ‘in-the-works‘ extensions to the IEEE 1149.1 test access standard, called IJTAG (Internal JTAG) and SJTAG (System JTAG).
The Internal JTAG effort seeks to standardize the access to ‘internal instruments’ of all sorts that may reside on a single [...]

I mentioned in another post just after ITC 2006, that I’d met Ben Bennetts for the first time. We had breakfast, and talked a bit about this blog I was trying to start up. It was an introductory conversation, but secretly, I was hoping to eventually convince him to work up some material [...]