Archive for NoC
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It’s that time of year again: goodbye 2008, hello 2009. How fun for me, the presumptive lonely voice in this quiet little corner of the EDA wilderness, design-for-test, right? BTW, today marks 3 years of DFT Digest -readership grew 50-100% this year, depending upon which numbers you’re looking at. Not bad - hopefully you’ll continue to read, and I’ll continue to compel you.
The rest of the industry talks about ESL, dead DFM companies, the next killer engineering app (energy), white-spaces, and the battle of the PU’s (CPU vs GPU); what’s happening in DFT?
I’m learning new things every day. Just recently, a friend of mine asked if I’d like to review a few papers for this year’s ITC. Being a part of the organizing committee, her areas are microprocessor test, SoC test, and NoC test.
Feeling a bit ignorant, I asked, “uhh, what’s ‘NoC’?”. “Network on Chip” [...]