Archive for Power-aware Test
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Magma may have come up with the most unique announcement last month - ATPG that fits inextricably within the Talus implementation tool suite. Not to be outdone, Synopsys came out with a couple of their own.
First was the announcement of low power management for manufacturing test. This effort seems to [...]
One of the areas of DFT development pointed out by Richard Quinnell of Test & Measurement World in his article entitled “Vendors pursue DFT strategies“, part of T&M’s DAC roundup, was test for ‘low-power designs’. Another term gaining traction for the process of coming up with these ‘low-power designs’ is ‘Power-Aware Design’. In [...]
Tonight there will be all manner of kids, big and small, traipsing through your neighborhood, masquerading as one thing or another. Be kind, or be tricked… Last week, at ITC, I felt a little like a trick-or-treater, walking around dressed up like a real DFT engineer.
Well, yes, I am a DFT engineer, and I [...]
I’ve run across a couple of items in my reading lately about concerns with test-mode power. Not that it’s a new issue, but sometimes when you’re looking for something else, a subject will jump out you a couple of times, causing you to take notice.
Much has been studied and written about test-mode power consumption in [...]
I’ve just been searching around for DFM related material, and I keep seeing DFT being mentioned as a critical component of DFM, so I’ll just keep on mentioning it here.
The latest article I find (and I guess it’s not new, but it’s dated 7/6/2006, which is new enough) is by Ron Wilson at EDN, and [...]