DFT Digest

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…let there be no doubt.

As a west coast USA native, like many Americans, I’m a little myopic – I admit it. But it’s never too late to change, right? Well, today, I confess to you all that I missed blogging about what appears to be a very interesting DFT/Test-related event that has just concluded: the seventeenth Asian Test Symposium. This was a 4-day event, in “snow[y] and cold” Sapporo, Japan.

System Verilog was signed off as a standard by IEEE in late 2005. In the 2-1/2 years since, front-end design tools for synthesis and verification have been making significant strides in support of the standard – not without limitations and missteps – but the effort is there. Progress has been made. So [...]

In a couple of previous posts, here, and here, I started discussing different design-for-test tools – you know, other than your run-of-the-mill ATPG and BIST tools. In the last post, I talked about a couple of tools that are targeted for the RTL domain. Now I’d like to mention some DFT-related products that [...]

Design-for-test is a rapidly expanding task which is becoming more integrated with the design flow as time goes on. As I mentioned in my previous post, there are DFT-related tools spanning the range from RTL to the extreme back-end (which fall into the DFM category, IMHO). I thought I’d talk a little [...]

If I may state the obvious, I am one guy, who has led one career, and therefore has a limited base of experience from which to draw. So when it comes to writing about Design-for-Test methodology and tools, those of you reading are getting a fairly narrow view of the wide world of DFT. [...]