Archive for RTL
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DFT Tools and System Verilog
System Verilog was signed off as a standard by IEEE in late 2005. In the 2-1/2 years since, front-end design tools for synthesis and verification have been making significant strides in support of the standard - not without limitations and missteps - but the effort is there. Progress has been made. So [...]
There are other DFT tools, and testers!
In a couple of previous posts, here, and here, I started discussing different design-for-test tools - you know, other than your run-of-the-mill ATPG and BIST tools. In the last post, I talked about a couple of tools that are targeted for the RTL domain. Now I’d like to mention some DFT-related products that [...]
RTL Design-for-Test
Design-for-test is a rapidly expanding task which is becoming more integrated with the design flow as time goes on. As I mentioned in my previous post, there are DFT-related tools spanning the range from RTL to the extreme back-end (which fall into the DFM category, IMHO). I thought I’d talk a little [...]
There are other DFT tools, too!
If I may state the obvious, I am one guy, who has led one career, and therefore has a limited base of experience from which to draw. So when it comes to writing about Design-for-Test methodology and tools, those of you reading are getting a fairly narrow view of the wide world of DFT. [...]
