Archive for Scan/ATPG
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Secure Design-for-Test
I was perusing the latest version of IEEE Design & Test, which focuses on ICs for Secure Embedded Computing, and it reminded me of a small flap a couple years back about the security, or lack thereof, of scan chains (Scan design called portal for hackers, EETimes, 10/25/2004). Although I haven’t personally noticed any [...]
Is at-speed scan enough? Audience says yes… panel split.
The stream of ITC-related press releases has come and gone, and I do plan on discussing more of them, but in between, I’d like to continue to offer some observations of people who were there - something exclusive, that you won’t find anywhere else but DFT Digest.
One such person is Teresa McLaurin, DFT manager at [...]
ATPG Wars - Magma comes back swinging…
One of the announcements from Test Week’s onslaught of test-related press releases from EDA vendors was Magma’s roll-out of Talus ATPG and Talus ATPG-X.  A couple of interesting things about this product:
1) Its tight integration into the Talus toolset means that it is a Magma user’s tool only. So Magma is marketing it to about [...]
Magma DFT: It’s alive!
Remember way back, this time last year, there were rumors about that Magma had abandoned their design-for-test tools? First, there was a post over at DeepChip, about the cancellation of their test program. Less than a week later, Richard Goering at EE Times wrote an article stating that, according to Magma marketing folk, Magma did [...]
DFT discussion fires up!
Wow - go away for a month and what happens? The readers take over! And that’s a good thing - it’s exactly what I’d like to happen.
For those of you that just look at the front page of DFT Digest, there has been some interesting discussion happening in the comments section of my [...]
