Archive for Scan/ATPG
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DFT discussion fires up!
Wow - go away for a month and what happens? The readers take over! And that’s a good thing - it’s exactly what I’d like to happen.
For those of you that just look at the front page of DFT Digest, there has been some interesting discussion happening in the comments section of my [...]
DFM, DFT and diagnostics data
In my DAC and DFT - post #2, I linked to an article at Test & Measurement World, that briefly outlined a few different ‘new’ DFT technologies being pursued by the big EDA companies. One of these areas was termed volume diagnostics or defect diagnostics. This ‘new technology’, to me at least, is [...]
The Top 10 Rules of Scan Design
I don’t know if I ever mentioned it before, but a DFT blog was not my original objective for creating an IC design oriented website. In truth, a couple of buddies and I had visions of [...]
Design-With-Test… 2nd sighting
Another article, this by Sanjiv Teneja of Cadence Design Systems, promoting DWT, or “Design-With-Test” has been posted over at Test & Measurement, as a guest commentary. I blogged a few weeks ago about a similar article by another marketing man from the same company. I smell a conspiracy! Just kidding, go to [...]
Design-With-Test?
Very interesting article over at embedded.com, by Tom Jackson of Cadence Design Systems. He makes some excellent points about the necessity of being aware of power consumption throughout the design flow, including the insertion of test structures. But “Design-With-Test”? What he’s describing is what I thought was termed “Power Aware Design and [...]
