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Wang, Laung-Terng, Charles E. Stroud, Nur A. Touba
System-on-Chip Test Architectures (Systems on Silicon)
Morgan Kaufmann- Nov, 2007

I’ve previously reviewed VLSI Test Principles and Architectures, edited by L.T. Wang, Chen-Wen Wu, and Xiaoqing Wen, and I’ve got to say, that book along with System-on-Chip Test Architectures, for the price, put an amazing of information at the fingertips of Design, Test and DFT engineers. I’ve said this before in DFT Digest, and I’ll say it again. For the most part, engineering and technical books are prohibitively expensive.

As I was putting together a post with some recent DFT-related news, I came across a couple of links referencing recent work on an extension to the IEEE 1149.1 (a.k.a. JTAG). As I read about this impending standard, my interest was piqued, so I embarked on a hyper-google for “IEEE 1149.7″, and came to realize I had only experienced the tip of an iceberg of press releases and product announcements - all from this month!