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Remember in my last post, where I told you how weird it was to suddenly be seeing all these references to 3D ID design technology? Well it didn’t stop. Literally, the day I posted that entry, I got the new issue of IEEE Design & Test – a special issue on, you guessed it: 3D IC Design and Test.

The same day, I was cleaning my desk, and found a couple of papers that I had printed out a couple of months ago and forgot about, from DATE ‘09. One was entitled Test Architecture and Optimization for Three-Dimensional SoC’s.

I always look forward to getting my new IEEE Design & Test magazine. It seems to consistently contain great articles that bring out leading edge practices in IC design and test. And, refreshingly for me, mostly test. Design-for-test. Good stuff.

The May/June issue that just arrived in my mailbox this week did not disappoint – it was part 2 of the special issue on IEEE Std 1500 and Its Usage – I blogged about the first part in February: Get to the core of the matter – how will you test that core?.

Wang, Laung-Terng, Charles E. Stroud, Nur A. Touba
System-on-Chip Test Architectures (Systems on Silicon)
Morgan Kaufmann- Nov, 2007

I’ve previously reviewed VLSI Test Principles and Architectures, edited by L.T. Wang, Chen-Wen Wu, and Xiaoqing Wen, and I’ve got to say, that book along with System-on-Chip Test Architectures, for the price, put an amazing of information at the fingertips of Design, Test and DFT engineers. I’ve said this before in DFT Digest, and I’ll say it again. For the most part, engineering and technical books are prohibitively expensive.

As I was putting together a post with some recent DFT-related news, I came across a couple of links referencing recent work on an extension to the IEEE 1149.1 (a.k.a. JTAG). As I read about this impending standard, my interest was piqued, so I embarked on a hyper-google for “IEEE 1149.7″, and came to realize I had only experienced the tip of an iceberg of press releases and product announcements – all from this month!