DFT Digest

It’s a full month after DAC has come and gone, so it’s kind of ridiculous to continue.  But I’ve been busy, lazy, on vacation, unmotivated - you pick, what the heck. I think maybe I need to write shorter posts more often, so I have less chance to procrastinate.

As I mentioned in my last post, I did have a couple more conversations with some test-related people.  I reported on Winterlogic last post - but right next to them on the show floor was TSSI.  Now TSSI’s been around a long time, but they’ve been thrrough so many incarnations, it’s like they were money being laundered.  I think I tried to trace their lineage once in a previous post, but bottom line is they’re back to being TSSI anyway.

The main product for TSSI, for years, has been TDS (Test Development Series).  Basically, it’s test vector translation software, but with algorithms built in to analyze event-based input (think VCD) at its core.  It’s modular in design, so it has several ‘readers’ for different simulator output formats, and many ‘writers’ to output vectors for one of many ATE formats.

TSSI introduced a new product at DAC - a tool called ‘FailMap‘ to visually compare ATE results (datalogs, which normally list pattern failures) with the the original simulation output, for easier debugging.  In addition to viewing the failures against the expected response from the simulation, the tool also provides the capability to mask the failures, or ‘learn’ the pattern (change the expected reponse to match actual silicon behavior, and rewrite it, thereby having a passing pattern).

To automate this capability can be a big plus while trying to quickly get patterns going on the tester when silicon first arrives, and real world operation doesn’t exactly match simulation (and face it, these days, with newer processes, it’s not uncommon)  Eventually you have to analyze the failures, but to get a quick initial screen going is tough without a tool like this…

Strolling down the aisle from there, I wandered into the Magma booth and asked about their ATPG tool.  But I’ve already told you that story.  Then I stopped in and chatted with L.T. Wang of SynTest.  Nice man.  I like the books he’s been publishing in the last few years (check out this one, and this one).  He told me he had been very busy, but was going to start writing some papers - to let people know that some of the techniques used for at-speed scan test have been patented (by SynTest).

My next stop was Genesys TestWare.  But this post is already too long.  So until next time…

Update: I could swear I published this article with a title, but then I noticed it coming up blank in my feed…

All along I’ve said that DAC’s not really my show, but it was more interesting this year, given the whole EDA Bloggers Birds of Feather deal. It inspired some good discussion, and I hope it becomes a repeated occurrence as we, the independent bloggers establish our value in the EDA community.

However, as I mentioned in a previous post, in my short walk about the floor, besides noting the distinct lack of ATPG in the Magma booth, I did have a couple of enjoyable conversations with some test-related exhibitors.

First, I talked to the guys in the WinterLogic booth. This was the first year at DAC for WinterLogic. Not quite a ‘household’ name in DFT circles, this company markets a product called Z01X, which is a “high-speed functional fault simulator for Verilog designs.”   Now, obtaining coverage by fault simulation, as a matter of practice for functional vectors, has taken a back seat in recent years to to the coverage achieved with structural methods (scan and BIST). But structural fault coverage is never a complete solution for the contemporary SoC, so the structural test-suite almost always has to be augmented with functional patterns.

Now the last time I actually used a fault simulator, nobody was talking about transition delay faults or bridge faults, but current fault simulators (I’ll go out on a limb here and say there are two: SynTest’s TurboFault and Z01X) cover both those classes of faults, and claim performance improvements and other added capabilities over previous generations of fault grading software.

One of the ways in which the folks at WinterLogic do believe they are unique is in their “test ordering and redundant test elimination capabilities“.  Z01X performs testability analysis on the design with respect to each test, then starting with the best coverage test, ranks and reorders the remaining tests after each run.  They claim to be able to reduce the overall test-set by as much as 50%.

This job of test optimization is many times tackled by the test or product engineer after a device has been in production to optimize test time. The decision to reorder or eliminate tests is based upon the statistics of how often particular tests catch defective parts, determined over time by testing many devices.  I’m sure a priori test selection in the pre-silicon domain by relative fault coverage is practiced also, in an ad hoc fashion, but Z01X would be the first productization of this as applied to functional pattern sets (ATPG tools also have this capability built-in, for structural patterns).

The folks in the Winterlogic DAC booth claimed to have produced excellent results with some very big customers with this technology.  After talking with them, I shuffled to the right (to the next booth) where TSSI was set up.  I’ll talk more about that in my next post, as well as my conversations with SynTest, Genesys TestWare, and LogicVision.

Stay tuned…

This week, I’ll try to pass along Design-for-Test related DAC news as it comes along…

First, it was announced today that the standards organization Accellera has selected Bruce Cory, a DFT manager at NVIDIA, to receive the 5th annual Technical Excellence Award, for leading the effort to bring the Open Compression Interface (OCI) to be approved by the Accellera membership, and continuing the effort to pass it as an IEEE standard (IEEE 1450.6.1, which I guess is an extension to the CTL standard).

The OCI standard will be an important step in establishing tool independence with regard to test data compression and diagnosis, while still protecting EDA vendor’s compression IP. Currently, once test compression IP from a certain vendor is incorporated into a design, ATPG tools from the same company must be used, as well as any other tool down the line (yield analysis, for example) that hopes to use ATPG data. This can get particularly problematic, especially in manufacturing and test environments that would have to support as many tool flows as there are test compression schemes.

Also today,  LogicVision announced the Dragonfly Test Platform, which will be demonstrated at DAC.  The new tool seems to be  an integration of existing, and in some cases improved versions of LogicVision’s embedded test tools addressing memory BIST and logic BIST, as well as debug and analysis tools such as Silicon Insight and Yield insight.

Earlier this month Genesys Testware announced announced yet another Design-for-X tool: Design-for-Leakage-Test (DFLT).  This is actually a feature added to their Hierarchical DFT tool, HiertestMaker, and addresses problems due to lack of testability around power-aware design structures, such as “power switches, and isolations gates”, and I assume level-shifters.  Here’s the press release.  Someone over at Genesys needs to work on their website: you may notice if you go to their homepage, the latest news is from ITC 2006, and the upcoming event is DAC 2007

Winterlogic, maker of the fault simulation tool Z01X will be exhibiting at DAC for the first time.

SynTest will also be exhibiting - stop by and congratulate L.T. Wang for being elected IEEE fellow earlier this year

Nothing test-related for Synopsys, and this is not necessarily DAC-related, but I have to brag that Synopsys has added a link to this blog on their Galaxy DFT page.  Mentor, Cadence?   Hello?