DFT Digest

You are browsing the archives of Test Compression.

Test Compression makes test vectors for efficient – I wish there was such a thing for schedules… ITC Day 2 for me seemed like a lot of running around, trying to find people, trying to avoid people [joking! really...], answering e-mails, phone calls, finding cell phone chargers… I missed a lot, but I suppose I was productive otherwise.

The most fun I had all day Wednesday was witnessing Panel 3 – Will Test Compression Run Out of Gas?

Let me hear you say yeah!

Karen Bartleson over at her blog, The Standards Game, issued an invitation to all who care*, to become a part of the balloting process for the IEEE P1450.6.1, “Standard for Describing On-Chip Scan Compression”, or Open Compression Interface. Karen has a short explanation of the idea behind the standard, and I’ve blogged about it here before. It was ratified by Accellera in October of 2006.

This week, I’ll try to pass along Design-for-Test related DAC news as it comes along…
First, it was announced today that the standards organization Accellera has selected Bruce Cory, a DFT manager at NVIDIA, to receive the 5th annual Technical Excellence Award, for leading the effort to bring the Open Compression Interface (OCI) to be approved [...]

Another article, this by Sanjiv Teneja of Cadence Design Systems, promoting DWT, or “Design-With-Test” has been posted over at Test & Measurement, as a guest commentary. I blogged a few weeks ago about a similar article by another marketing man from the same company. I smell a conspiracy! Just kidding, go [...]

The Cell Broadband Engine, that is.  Neat article over at Evaluation Engineering.  Written bt DFT engineers from IBM and Brion Keller from Cadence, the article details the overall test approach for this multicore SoC.   I don’t know how new the article is, since Cadence released this PR in April of last year.  But it was [...]