DFT Digest

Let me hear you say yeah!

Karen Bartleson over at her blog, The Standards Game, issued an invitation to all who care*, to become a part of the balloting process for the IEEE P1450.6.1, “Standard for Describing On-Chip Scan Compression”, or Open Compression Interface.  Karen has a short explanation of the idea behind the standard, and I’ve blogged about it here before. It was ratified by Accellera in October of 2006.

Why is this standard important? Because today, if you decide to implement test compression on your device, you are stuck with the tool vendor that sold you that IP - from cradle to grave.  I think of test compression as a three-part solution: the logical IP that is implemented on-chip, the ATPG tool that creates the vectors, and the yield analysis tool that interprets failures in those vectors.  Since the hardware of the first part is proprietary, the only way for the software of the second and third parts to understand it is for the whole solution to come from the same vendor.

I can think of several ways this is problematic.  Can you?  The short story is that interoperability is better, and this is the intent of IEEE P1451.6.1.

* I think, in this case, all who care should read “all companies and/or organizations who care”.  I don’t believe the balloting is open to individuals. Someone correct me if I’m wrong, and I’ll pay the $40 to vote…

This week, I’ll try to pass along Design-for-Test related DAC news as it comes along…

First, it was announced today that the standards organization Accellera has selected Bruce Cory, a DFT manager at NVIDIA, to receive the 5th annual Technical Excellence Award, for leading the effort to bring the Open Compression Interface (OCI) to be approved by the Accellera membership, and continuing the effort to pass it as an IEEE standard (IEEE 1450.6.1, which I guess is an extension to the CTL standard).

The OCI standard will be an important step in establishing tool independence with regard to test data compression and diagnosis, while still protecting EDA vendor’s compression IP. Currently, once test compression IP from a certain vendor is incorporated into a design, ATPG tools from the same company must be used, as well as any other tool down the line (yield analysis, for example) that hopes to use ATPG data. This can get particularly problematic, especially in manufacturing and test environments that would have to support as many tool flows as there are test compression schemes.

Also today,  LogicVision announced the Dragonfly Test Platform, which will be demonstrated at DAC.  The new tool seems to be  an integration of existing, and in some cases improved versions of LogicVision’s embedded test tools addressing memory BIST and logic BIST, as well as debug and analysis tools such as Silicon Insight and Yield insight.

Earlier this month Genesys Testware announced announced yet another Design-for-X tool: Design-for-Leakage-Test (DFLT).  This is actually a feature added to their Hierarchical DFT tool, HiertestMaker, and addresses problems due to lack of testability around power-aware design structures, such as “power switches, and isolations gates”, and I assume level-shifters.  Here’s the press release.  Someone over at Genesys needs to work on their website: you may notice if you go to their homepage, the latest news is from ITC 2006, and the upcoming event is DAC 2007

Winterlogic, maker of the fault simulation tool Z01X will be exhibiting at DAC for the first time.

SynTest will also be exhibiting - stop by and congratulate L.T. Wang for being elected IEEE fellow earlier this year

Nothing test-related for Synopsys, and this is not necessarily DAC-related, but I have to brag that Synopsys has added a link to this blog on their Galaxy DFT page.  Mentor, Cadence?   Hello?