DFT Digest

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The Cell Broadband Engine, that is.  Neat article over at Evaluation Engineering.  Written bt DFT engineers from IBM and Brion Keller from Cadence, the article details the overall test approach for this multicore SoC.   I don’t know how new the article is, since Cadence released this PR in April of last year.  But it was [...]

Very interesting article over at embedded.com, by Tom Jackson of Cadence Design Systems. He makes some excellent points about the necessity of being aware of power consumption throughout the design flow, including the insertion of test structures. But “Design-With-Test”? What he’s describing is what I thought was termed “Power Aware Design and [...]

It’s been a long time (2 weeks) since my last post; I’ve been enjoying my holiday, thank you very much. I hope you all have too!
It’s actually exactly 1 year since my first post, even though I didn’t get real active until August or so, and didn’t start really telling anyone about the blog [...]

I started this thread a ccouple of weeks ago, a post – something about writing a DFT plan. My contention was that a testability plan is an outgrowth of the test plan, adding efficiency and coverage.
One comment (thanks, Craig!) on that post got us off to a good start by defining some of the [...]

Today, Accellera has approved the Open Compression Interface standard (OCI version 1.0). See the EE Times article by Richard Goering here.
Back in Test Compression Series – Installment #2, I made brief mention of OCI, which is an effort that was undertaken by Accellera due to a need in the industry for flexibilty in test [...]