DFT Digest

I’ve had some feedback on this website that pointed out that although the concept is good, the information people are looking for is not easy to find (or not there!). My mission for the near future is to try to address that.

One of the ways (that I sort of lucked into) is the addition of the DFT Forum as an affiliated website, in cooperation with Siyad Ma. I believe once we get enough people signed up and sharing information, that DFT Forum will be a valuable resource for anyone wading in the waters of design-for-test.

Another way to make information more accessible is my new effort: The Tutorials/Resources page. If you look over on the right-hand sidebar, under the ‘Pages’ heading, you’ll see a link called ‘Tutorials/Resources‘. This will lead to a more organized (maybe) set of pages of my own writing, as well as links to other material available on the web on a variety of design-for-test subjects. It’s a work in progress, I’m going to try to add a section or do every month. Cross your fingers, and let me know what you think…

The other thing that I’m going to try and do is go back and re-categorize some of my posts, so that information within those posts are easier to find.

I don’t know if I ever mentioned it before, but a DFT blog was not my original objective for creating an IC design oriented website. In truth, a couple of buddies and I had visions of a well-oiled EDA forum site with experienced professionals trading tricks of the trade – I was just going to be the design for test moderator. But, as always, engineers get busy or distracted, and well, we haven’t pulled it off yet.

However, there are other websites with forums out there. A couple come to mind: design-for-test.com (this would be my preferred place to post a DFT question, as it’s run by an expert), edaboard.com, and edacafe.com also has a forum. One thing about these forums – it seems DFT still remains somewhat an esoteric art. Some of the questions: “Why DFT?”, “What is DFT?”, or “Please state all the DFT design rules and their solutions…”

Once again, design for test is often lobbed to a junior member of the design team, who more often than not, has no idea where to start. And since a majority of our engineering schools spend next to no time on test, well, here we are.

Dave Letterman counts down from 10 to 1, but I’m pretty much a bigendian digital DFT engineer, so I’m going from 9 to 0. So without further ado, I present to you my ‘Top 10 Scan Design Rules’:

9 - Melting pot: NOT! don’t mix scan cell types in a design
8 - Primary input controlled resets
7 - Primary input controlled clocks
6 - Fight the scourge of internal tri-state busses
5 - Mixing clocks and data is racy
4 - Avoid combinational feedback
3 - Remember your memories
2 - Proceed with caution (from one clock domain to another)
1 - Know your ATE
0 - Scan everything

The longer winded explanations are after the click. Have a read, and let me know what you think! (more…)